Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TQFP 44 (10x10) 8-Bit 20 MHz I/O number 36

 2010-2011 Microchip Technology Inc. DS41418B-page 23

PIC16(L)F707

Bank 2

100h

(2)

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx

101h TMR0 Timer0 Module Register 0000 0000 0000 0000

102h

(2)

PCL Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000

103h

(2)

STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu

104h

()

FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu

105h TACON TMRAON

— TACS TASE TAPSA TAPS2 TAPS1 TAPS0 0-00 0000 0-00 0000

106h CPSBCON0 CPSBON CPSBRM

— — CPSBRNG1 CPSBRNG0 CPSBOUT TBXCS 00-- 0000 00-- 0000

107h CPSBCON1

— — — — CPSBCH3 CPSBCH2 CPSBCH1 CPSBCH0 ---- 0000 ---- 0000

108h CPSACON0 CPSAON CPSARM

— — CPSARNG1 CPSARNG0 CPSAOUT TAXCS 0--- 0000 0--- 0000

109h CPSACON1

— — — — CPSACH3 CPSACH2 CPSACH1 CPSACH0 ---- 0000 ---- 0000

10Ah

(1),(2)

PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000

10Bh

(2)

INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u

10Ch PMDATL Program Memory Read Data Register Low Byte xxxx xxxx uuuu uuuu

10Dh PMADRL Program Memory Read Address Register Low Byte xxxx xxxx uuuu uuuu

10Eh PMDATH

— — Program Memory Read Data Register High Byte --xx xxxx --uu uuuu

10Fh PMADRH

— — — Program Memory Read Address Register High Byte ---x xxxx ---u uuuu

110h TMRA TimerA Module Register 0000 0000 0000 0000

111h TBCON TMRBON

— TBCS TBSE TBPSA TBPS2 TBPS1 TBPS0 0-00 0000 0-00 0000

112h TMRB TimerB Module Register 0000 0000 0000 0000

113h DACCON0 DACEN DACLPS DACOE

— DACPSS1 DACPSS0 — — 000- 00-- 000- 00--

114h DACCON1

— — — DACR4 DACR3 DACR2 DACR1 DACR0 ---0 0000 ---0 0000

TABLE 2-2: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR, BOR

Value on all

other

resets

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the

upper byte of the program counter.

2: These registers can be addressed from any bank.

3: Accessible only when SSPM<3:0> = 1001.