Datasheet

PIC16(L)F707
DS41418B-page 220  2010-2011 Microchip Technology Inc.
FIGURE 25-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
FIGURE 25-9: BROWN-OUT RESET TIMING AND CHARACTERISTICS
VDD
MCLR
Internal
POR
PWRT
Time-out
OSC
Start-Up Time
Internal Reset
(1)
Watchdog Timer
33
32
30
31
34
I/O pins
34
Note 1: Asserted low.
Reset
(1)
VBOR
VDD
(Device in Brown-out Reset) (Device not in Brown-out Reset)
33
(1)
Note 1: 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’. 2 ms
delay if PWRTE
= 0 and VREGEN = 1.
Reset
(due to BOR)
VBOR and VHYST
37