Datasheet
PIC16(L)F707
DS41418B-page 22 2010-2011 Microchip Technology Inc.
Bank 1
80h
(2)
INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx
81h OPTION_REG RBPU
INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
82h
(2)
PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
83h
(2)
STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu
84h
(2)
FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu
85h TRISA PORTA Data Direction Register 1111 1111 1111 1111
86h TRISB PORTB Data Direction Register 1111 1111 1111 1111
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
88h TRISD PORTD Data Direction Register 1111 1111 1111 1111
89h TRISE
— — — — ‘1’ TRISE2 TRISE1 TRISE0 ---- 1111 ---- 1111
8Ah
(1),(2)
PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
8Bh
(2)
INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u
8Ch PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh PIE2 TMR3GIE TMR3IE TMRBIE TMRAIE
— — — CCP2IE 0000 ---0 0000 ---0
8Eh PCON
— — — — — —PORBOR ---- --qq ---- --uu
8Fh T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/
DONE
T1GVAL T1GSS1 T1GSS0 0000 0x00 uuuu uxuu
90h OSCCON
— — IRCF1 IRCF0 ICSL ICSS — — --10 00-- --10 uu--
91h OSCTUNE
— — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 --00 0000 --00 0000
92h PR2 Timer2 Period Register 1111 1111 1111 1111
93h SSPADD Synchronous Serial Port (I
2
C mode) Address Register 0000 0000 0000 0000
93h
(3)
SSPMSK Synchronous Serial Port (I
2
C mode) Address Mask Register 1111 1111 1111 1111
94h SSPSTAT SMP CKE D/A
PSR/WUA BF 0000 0000 0000 0000
95h WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 1111 1111
96h IOCB IOCB7 IOCB6 IOCB5 IOCB4 IOCB3 IOCB2 IOCB1 IOCB0 0000 0000 0000 0000
97h T3CON TMR3CS1 TMR3CS0 T3CKPS1 T3CKPS0
— T3SYNC —TMR3ON0000 -0-0 uuuu -u-u
98h TXSTA CSRC TX9 TXEN SYNC
— BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000
9Ah TMR3L Holding Register for the Least Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu
9Bh TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu
9Ch APFCON
— — — — — — SSSEL CCP2SEL ---- --00 ---- --00
9Dh FVRCON FVRRDY FVREN
— — CDAFVR1 CDAFVR0 ADFVR1 ADFVR0 x000 0000 x000 0000
9Eh T3GCON TMR3GE T3GPOL T3GTM T3GSPM T3GGO/
DONE
T3GVAL T3GSS1 T3GSS0 0000 0x00 uuuu uxuu
9Fh ADCON1
— ADCS2 ADCS1 ADCS0 — — ADREF1 ADREF0 -000 --00 -000 --00
TABLE 2-2: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR, BOR
Value on all
other
resets
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the
upper byte of the program counter.
2: These registers can be addressed from any bank.
3: Accessible only when SSPM<3:0> = 1001.