Datasheet

 2010-2011 Microchip Technology Inc. DS41418B-page 177
PIC16(L)F707
19.2.10 CLOCK SYNCHRONIZATION
When the CKP bit is cleared, the SCL output is held
low once it is sampled low. Therefore, the CKP bit will
not stretch the SCL line until an external I
2
C master
device has already asserted the SCL line low. The
SCL output will remain low until the CKP bit is set and
all other devices on the I
2
C bus have released SCL.
This ensures that a write to the CKP bit will not violate
the minimum high time requirement for SCL
(Figure 19-14).
19.2.11 SLEEP OPERATION
While in Sleep mode, the I
2
C module can receive
addresses of data, and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if SSP interrupt is enabled).
FIGURE 19-14: CLOCK SYNCHRONIZATION TIMING
SDA
SCL
DX-1DX
WR
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SSPCON
CKP
Master device
deasserts clock
Master device
asserts clock