Datasheet

PIC16(L)F707
DS41418B-page 114  2010-2011 Microchip Technology Inc.
14.1 TimerA/B Operation
The TimerA/B modules can be used as either 8-bit tim-
ers or 8-bit counters. Additionally, the modules can also
be used to set Timer1’s/Timer3’s period of measure-
ment for the capacitive sensing modules via Timer1’s
or Timer3’s gate feature.
14.1.1 8-BIT TIMER MODE
The TimerA/B modules will increment every instruction
cycle, if used without a prescaler. 8-bit Timer mode is
selected by clearing the TMRxCS bit of the TxCON
registers.
When TMRx is written, the increment is inhibited for
two instruction cycles immediately following the write.
14.1.2 8-BIT COUNTER MODE
In 8-bit Counter mode, the TimerA/B modules will
increment on every rising or falling edge of the TxCKI
pin or the Capacitive Sensing Oscillator (CPSxOSC)
signal. 8-bit Counter mode using the TxCKI pin is
selected by setting the TMRxCS bit of the TxCON
register to ‘1’ and resetting the TxXCS bit in the
CPSxCON0 register to ‘0’. 8-bit Counter mode using the
Capacitive Sensing Oscillator (CPSxOSC) signal is
selected by setting the TMRxCS bit in the TxCON
register to ‘1’ and setting the TxXCS bit in the
CPSxCON0 register to ‘1’.
The rising or falling transition of the incrementing edge
for either input source is determined by the TMRxSE bit
in the TxCON register.
14.1.3 SOFTWARE PROGRAMMABLE
PRESCALER
For TimerA/B modules, the software programmable
prescaler is exclusive to the Timer. The prescaler is
enabled by clearing the TMRxPSA bit of the TxCON
register.
There are 8 prescaler options for TimerA/B modules
ranging from 1:2 to 1:256. The prescale values are
selectable via the TMRxPS<2:0> bits of the TxCON
register for TimerA/B. In order to have a 1:1 prescaler
value for the TimerA/B modules, the prescaler must be
disabled.
The prescaler is not readable or writable. When the
prescaler is enabled or assigned to the Timer module, all
instructions writing to the TMRx register will clear the
prescaler. Enabling the TimerA/B modules also clears
the prescaler.
14.1.4 TIMERA/B INTERRUPT
TimerA/B will generate an interrupt when the
corresponding TMR register overflows from FFh to
00h. The TMRxIF interrupt flag bit of the PIR2 register
is set every time the TMRx register overflows. These
interrupt flag bits are set regardless of whether or not
the relative Timer interrupt is enabled. The interrupt flag
bits can only be cleared in software. The TimerA/B
interrupt enable bits are the TMRxIE in the PIE2
register.
14.1.5 USING TIMERA/B WITH AN
EXTERNAL CLOCK
When TimerA/B is in Counter mode, the
synchronization of the TxCKI input and the TMRx
register is accomplished by sampling the prescaler
output on the Q2 and Q4 cycles of the internal phase
clocks. Therefore, the high and low periods of the
external clock source must meet the timing
requirements as shown in Section 25.0 “Electrical
Specifications”.
14.1.6 TIMER ENABLE
Operation of TimerA/B is enabled by setting the
TMRxON bit of the TxCON register. When the module
is disabled, the value in the TMRx register is
maintained. Enabling the TMRx module will reset the
prescaler used by the counter.
14.1.7 OPERATION DURING SLEEP
TimerA and TimerB cannot operate while the processor
is in Sleep mode. The contents of the TMRx registers
will remain unchanged while the processor is in Sleep
mode.
TABLE 14-1: CPSOSC/TIMER
ASSOCIATION
Cap Sense
Oscillator
Divider Timer
Period
Measurement
CPS A TimerA Timer1
CPS B TimerB Timer3
Note: The value written to the TMRx register can
be adjusted, in order to account for the
two instruction cycle delay when TMRx is
written.
Note: TimerA/B interrupts cannot wake the
processor from Sleep since the timer is
frozen during Sleep.