Datasheet

PIC16(L)F707
DS41418B-page 102  2010-2011 Microchip Technology Inc.
FIGURE 13-1: TIMER1/TIMER3 BLOCK DIAGRAM
TMRxH TMRxL
TxSYNC
TxCKPS<1:0>
Prescaler
1, 2, 4, 8
0
1
Synchronized
clock input
2
Set flag bit
TMRxIF on
Overflow
TMRx
(2)
TMRxON
Note 1: ST Buffer is high speed type when using TxCKI.
2: Timer1/3 register increments on rising edge.
3: Synchronize does not operate while in Sleep.
4: Timer1 gate source is TimerA. Timer3 gate source is TimerB. Refer to Table 13-1.
5: Timer1 clock source is CPSAOSC. Timer3 clock source is CPSBOSC. Refer to Table 13-1.
6: Timer3 does not have a T3OSC circuit. There is no T3OSCEN bit. Timer3 can operate from T1OSC.
TxG
T1OSC
F
OSC
Internal
Clock
T1OSO/T1CKI
T1OSI
T1OSCEN
1
0
TxCKI
TMRxCS<1:0>
(1)
Synchronize
(3)
det
Sleep input
TMRxGE
0
1
00
01
10
11
From TimerA/B
From Timer2
TxGPOL
D
Q
CK
Q
0
1
TxGVAL
TxGTM
Single Pulse
Acq. Control
TxGSPM
TxGGO/DONE
TxGSS<1:0>
EN
OUT
11
10
00
00
FOSC/4
Internal
Clock
From WDT
Overflow
Match PR2
Overflow
(4)
R
D
EN
Q
Q1
RD
TXGCON
Data Bus
det
Interrupt
TMRxGIF
Set
TxCLK
FOSC/2
Internal
Clock
D
EN
Q
TxG_IN
(6)
Cap. Sense
(5)
Oscillator A/B
TABLE 13-1: CPSOSC/TIMER
ASSOCIATION
Period
Measurement
Cap Sense
Oscillator
Divider Timer
(Gate Source)
Timer1 CPS A TimerA
Timer3 CPS B TimerB