PIC16(L)F707 Data Sheet 40/44-Pin, Flash Microcontrollers with nanoWatt XLP and mTouch™ Technology 2010-2011 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC16(L)F707 40/44-Pin, Flash Microcontrollers with nanoWatt XLP and mTouch™ Technology Devices included in this data sheet: • PIC16F707 • PIC16LF707 High-Performance RISC CPU: • Only 35 Single-Word Instructions to Learn: - All single-cycle instructions except branches • Operating Speed: - DC – 20 MHz clock input - DC – 200 ns instruction cycle • 8K x 14 Words of Flash Program Memory • 363 Bytes of Data Memory (SRAM) • Interrupt Capability • 8-Level Deep Hardware Stack • Direct, Indirect and Relative Addre
PIC16(L)F707 • Synchronous Serial Port (SSP): - SPI (Master/Slave) - I2C™ (Slave) with Address Mask • Voltage Reference module: - Fixed Voltage Reference (FVR) with 1.024V, 2.048V and 4.
PIC16(L)F707 Pin Diagrams PIC16F707 PIC16LF707 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 RA6/OSC2/CLKOUT/CPSB1/VCAP(3) RA7/OSC1/CLKIN/CPSB0 VSS VSS NC VDD RE2/AN7/CPSA7 RE1/AN6/CPSA6 RE0/AN5/CPSA5 RA5/AN4/CPSA4/SS(2)/VCAP(3) RA4/CPSA3/T0CKI/TACKI CCP2(1)/CPSB11/AN9/RB3 NC CPSB12/AN11/RB4 T3CKI/T1G/CPSB13/AN13/RB5 ICSPCLK/CPSB14/RB6 ICSPDAT/CPSB15/RB7 VPP/MCLR/RE3 VCAP(3)/SS(2)/AN0/RA0 CPSA0/AN1/RA1 DACOUT/CPSA1/AN2/RA2 CPSA2/VREF/AN3/RA3 DT/RX/CPSA11/RC
PIC16(L)F707 Pin Diagrams 44 43 42 41 40 39 38 37 36 35 34 RC6/CPSA10/TX/CK RC5/CPSA9/SDO RC4/SDI/SDA RD3/CPSA8 RD2/CPSB7 RD1/CPSB6 RD0CPSB5/T3G RC3//SCK/SCL RC2CPSB4/CCP1/TBCKI RC1/CPSB3/T1OSI/CCP2(1) NC 44-PIN TQFP PIC16F707 PIC16LF707 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 NC RC0/T1OSO/T1CKI/CPSB2 RA6/OSC2/CLKOUT/CPSB1/VCAP(3) RA7/OSC1/CLKIN/CPSB0 VSS VDD RE2/AN7/CPSA7 RE1/AN6/CPSA6 RE0/AN5/CPSA5 RA5/AN4/CPSA4/SS(2)/VCAP(3) RA4/CPSA3/T0CKI/TACKI
PIC16(L)F707 Pin Diagrams PIC16F707 PIC16LF707 30 29 28 27 26 25 24 23 22 1 11 12 13 14 15 16 17 18 19 202 1 2 3 4 5 6 7 8 9 10 RC0/CPSB2/T1OSO/T1CKI RA6/OSC2/CLKOUT/CPSB1/VCAP(3) RA7/OSC1/CLKIN/CPSB0 VSS VDD RE2/AN7/CPSA7 RE1/AN6/CPSA6 RE0/AN5/CPSA5 RA5/AN4/CPSA4/SS(2)/VCAP(3) RA4/CPSA3/T0CKI/TACKI CCP2(1)/CPSB11/AN9/RB3 CPSB12/AN11/RB4 T3CKI/T1G/CPSB13/AN13/RB5 ICSPCLK/CPSB14/RB6 ICSPDAT/CPSB15/RB7 VPP/MCLR/RE3 VCAP/SS(2)/AN0/RA0 CPSA0/AN1/RA1 DACOUT/CPSA1/AN2/RA2 CPSA2/VREF/AN3/RA3 DT/RX/CPSA11/RC
PIC16(L)F707 — Basic AN0 Pull-up DAC Y Interrupt A/D 17 SSP ANSEL 19 AUSART 40-Pin UQFN 19 CCP 44-Pin QFN 2 Timers 44-Pin TQFP RA0 Cap Sensor 40-Pin PDIP 40/44-PIN ALLOCATION TABLE FOR PIC16F707/PIC16LF707 I/O TABLE 1: — — — SS(3) — — VCAP(4) RA1 3 20 20 18 Y AN1 — CPSA0 — — — — — — — RA2 4 21 21 19 Y AN2 DACOUT CPSA1 — — — — — — — RA3 5 22 22 20 Y AN3/ VREF VREF CPSA2 — — — — — — — RA4 6 23 23 21 Y — — CPSA3 T0CKI/ T
PIC16(L)F707 40-Pin UQFN A/D DAC Cap Sensor Timers CCP AUSART SSP Interrupt Pull-up Basic 7, 8, 28 7, 26 — — — — — — — — — VDD 6, 30, 31 6, 27 — — — — — — — — — VSS VDD 11, 32 Vss 12, 31 6, 29 Note ANSEL 44-Pin QFN 7, 28 40-Pin PDIP 44-Pin TQFP 40/44-PIN ALLOCATION TABLE FOR PIC16F707/PIC16LF707 I/O TABLE 1: 1: Pull-up activated only with external MCLR configuration. 2: RC1 is the default pin location for CCP2.
PIC16(L)F707 Table of Contents 1.0 Device Overview ....................................................................................................................................................................... 13 2.0 Memory Organization ................................................................................................................................................................ 19 3.0 Resets ...........................................................................................
PIC16(L)F707 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.
PIC16(L)F707 NOTES: DS41418B-page 12 2010-2011 Microchip Technology Inc.
PIC16(L)F707 1.0 DEVICE OVERVIEW The PIC16(L)F707 devices are covered by this data sheet. They are available in 40/44-pin packages. Figure 1-1 shows a block diagram of the PIC16(L)F707 devices. Table 1-1 shows the pinout descriptions. 2010-2011 Microchip Technology Inc.
PIC16(L)F707 FIGURE 1-1: PIC16(L)F707 BLOCK DIAGRAM PORTA Configuration 13 Program Counter Flash Program Memory Program Bus 8 Level Stack (13-bit) 14 RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 8 Data Bus RAM PORTB 9 RAM Addr RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 Addr MUX Instruction Instruction Reg reg 7 Direct Addr 8 Indirect Addr FSR reg Reg FSR STATUS STATUS Reg reg PORTC 8 3 Power-up Timer Oscillator Start-up Timer Instruction Decode Decodeand & Control OSC2/CLKOUT Timing Generation PORTD 8 W
PIC16(L)F707 TABLE 1-1: PIC16(L)F707 PINOUT DESCRIPTION Name RA0/AN0/SS/VCAP RA1/AN1/CPSA0 RA2/AN2/CPSA1/DACOUT RA3/AN3/VREF/CPSA2 RA4/CPSA3/T0CKI/TACKI RA5/AN4/CPSA4/SS/VCAP RA6/OSC2/CLKOUT/VCAP/ CPSB1 RA7/OSC1/CLKIN/CPSB0 RB0/AN12/CPSB8/INT RB1/AN10/CPSB9 Function Input Type RA0 TTL AN0 AN Output Type Description CMOS General purpose I/O. — SS ST — VCAP Power Power RA1 TTL AN1 AN A/D Channel 0 input. Slave Select input. Filter capacitor for Voltage Regulator (PIC16F only).
PIC16(L)F707 TABLE 1-1: PIC16(L)F707 PINOUT DESCRIPTION (CONTINUED) Name RB2/AN8/CPSB10 RB3/AN9/CPSB11/CCP2 RB4/AN11/CPSB12 RB5/AN13/CPSB13/T1G/T3CKI RB6/ICSPCLK/ICDCLK/CPSB14 RB7/ICSPDAT/ICDDAT/CPSB15 RC0/T1OSO/T1CKI/CPSB2 RC1/T1OSI/CCP2/CPSB3 RC2/CCP1/CPSB4/TBCKI RC3/SCK/SCL Function Input Type RB2 TTL Description CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. AN8 AN — A/D Channel 8 input.
PIC16(L)F707 TABLE 1-1: PIC16(L)F707 PINOUT DESCRIPTION (CONTINUED) Name RC4/SDI/SDA RC5/SDO/CPSA9 RC6/TX/CK/CPSA10 RC7/RX/DT/CPSA11 RD0/CPSB5/T3G RD1/CPSB6 RD2/CPSB7 RD3/CPSA8 RD4/CPSA12 RD5/CPSA13 RD6/CPSA14 RD7/CPSA15 RE0/AN5/CPSA5 RE1/AN6/CPSA6 RE2/AN7/CPSA7 RE3/MCLR/VPP VDD Function Input Type RC4 ST Output Type Description CMOS General purpose I/O. SDI ST — SPI data input. SDA I2C™ OD I2C™ data input/output. RC5 ST CMOS General purpose I/O.
PIC16(L)F707 TABLE 1-1: PIC16(L)F707 PINOUT DESCRIPTION (CONTINUED) Name VSS Function Input Type Output Type VSS Power — Legend: AN = Analog input or output TTL = TTL compatible input HV = High Voltage Note: Description Ground reference. CMOS = CMOS compatible input or output OD = Open Drain ST = Schmitt Trigger input with CMOS levels I2C™ = Schmitt Trigger input with I2C XTAL = Crystal levels The PIC16F707 devices have an internal low dropout voltage regulator.
PIC16(L)F707 2.0 MEMORY ORGANIZATION 2.1 Program Memory Organization The PIC16(L)F707 has a 13-bit program counter capable of addressing an 8K x 14 program memory space. The Reset vector is at 0000h and the interrupt vector is at 0004h.
PIC16(L)F707 TABLE 2-1: DATA MEMORY MAP FOR PIC16(L)F707 File Address Indirect addr.(*) 00h Indirect addr.(*) 80h Indirect addr.(*) 100h Indirect addr.
PIC16(L)F707 TABLE 2-2: Address SPECIAL FUNCTION REGISTER SUMMARY Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets Bank 0 00h(2) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx 01h TMR0 Timer0 Module Register 0000 0000 0000 0000 02h(2) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 03h(2) STATUS 0001 1xxx 000q quuu 04h(2) FSR Indirect
PIC16(L)F707 TABLE 2-2: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets Bank 1 80h(2) INDF 81h OPTION_REG 82h(2) PCL 83h(2) STATUS Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG TMR0CS IRP RP1 RP0 TMR0SE PSA PS2 xxxx xxxx xxxx xxxx PS1 PS0 1111 1111 1111 1111 0000 0000 0000 0000 DC C 0001 1xxx 000q quuu Pr
PIC16(L)F707 TABLE 2-2: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets Bank 2 100h(2) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx 101h TMR0 Timer0 Module Register 0000 0000 0000 0000 102h(2) PCL Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000 103h(2) STATUS 000q quuu IRP RP1 RP0
PIC16(L)F707 TABLE 2-2: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other resets Bank 3 180h(2) INDF 181h OPTION_REG 182h(2) PCL 183h(2) STATUS Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG TMR0CS IRP RP1 RP0 TMR0SE PSA PS2 xxxx xxxx xxxx xxxx PS1 PS0 1111 1111 1111 1111 0000 0000 0000 0000 DC C 0001 1xxx 000q quuu
PIC16(L)F707 2.2.2.1 STATUS Register The STATUS register, shown in Register 2-1, contains: • the arithmetic status of the ALU • the Reset status • the bank select bits for data memory (SRAM) The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic.
PIC16(L)F707 2.2.2.2 OPTION Register Note: The OPTION register, shown in Register 2-2, is a readable and writable register, which contains various control bits to configure: • • • • Timer0/WDT prescaler External RB0/INT interrupt Timer0 Weak pull-ups on PORTB REGISTER 2-2: To achieve a 1:1 prescaler assignment for Timer0, assign the prescaler to the WDT by setting PSA bit of the OPTION register to ‘1’. Refer to Section 13.3 “Timer1/3 Prescaler”.
PIC16(L)F707 2.2.2.3 PCON Register The Power Control (PCON) register contains flag bits (refer to Table 3-4) to differentiate between a: • Power-on Reset (POR) • Brown-out Reset (BOR) The PCON register bits are shown in Register 2-3.
PIC16(L)F707 2.3 PCL and PCLATH The Program Counter (PC) is 13 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 2-2 shows the two situations for the loading of the PC. The upper example in Figure 2-2 shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH).
PIC16(L)F707 2.5 EXAMPLE 2-2: Indirect Addressing, INDF and FSR Registers MOVLW MOVWF BANKISEL NEXT CLRF INCF BTFSS GOTO CONTINUE The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses data pointed to by the File Select Register (FSR). Reading INDF itself indirectly will produce 00h.
PIC16(L)F707 NOTES: DS41418B-page 30 2010-2011 Microchip Technology Inc.
PIC16(L)F707 3.0 RESETS The PIC16(L)F707 differentiates between various kinds of Reset: a) b) c) d) e) f) Power-on Reset (POR) WDT Reset during normal operation WDT Reset during Sleep MCLR Reset during normal operation MCLR Reset during Sleep Brown-out Reset (BOR) A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 3-1. Some registers are not affected in any Reset condition; their status is unknown on POR and unchanged in any other Reset.
PIC16(L)F707 TABLE 3-1: STATUS BITS AND THEIR SIGNIFICANCE POR BOR TO PD 0 x 1 1 Power-on Reset or LDO Reset 0 x 0 x Illegal, TO is set on POR 0 x x 0 Illegal, PD is set on POR 1 0 1 1 Brown-out Reset 1 1 0 1 WDT Reset 1 1 0 0 WDT Wake-up 1 1 u u MCLR Reset during normal operation 1 1 1 0 MCLR Reset during Sleep or interrupt wake-up from Sleep TABLE 3-2: Condition RESET CONDITION FOR SPECIAL REGISTERS(2) Program Counter STATUS Register PCON Register Power-o
PIC16(L)F707 3.1 MCLR 3.3 The PIC16(L)F707 has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a Reset does not drive the MCLR pin low. Voltages applied to the pin that exceed its specification can result in both MCLR Resets and excessive current beyond the device specification during the ESD event. For this reason, Microchip recommends that the MCLR pin no longer be tied directly to VDD.
PIC16(L)F707 3.4.2 WDT CONTROL The WDTE bit is located in the Configuration Word Register 1. When set, the WDT runs continuously. The PSA and PS<2:0> bits of the OPTION register control the WDT period. See Section 12.0 “Timer0 Module” for more information.
PIC16(L)F707 3.5 Brown-Out Reset (BOR) If VDD falls below VBOR for greater than parameter (TBOR) (see Section 25.0 “Electrical Specifications”), the brown-out situation will reset the device. This will occur regardless of VDD slew rate. A Reset is not ensured to occur if VDD falls below VBOR for more than parameter (TBOR). Brown-out Reset is enabled by programming the BOREN<1:0> bits in the Configuration register.
PIC16(L)F707 3.6 Time-out Sequence 3.7 On power-up, the time-out sequence is as follows: first, PWRT time-out is invoked after POR has expired, then OST is activated after the PWRT time-out has expired. The total time-out will vary based on oscillator configuration and PWRTE bit status. For example, in EC mode with PWRTE bit = 1 (PWRT disabled), there will be no time-out at all. Figure 3-5, Figure 3-6 and Figure 3-7 depict time-out sequences.
PIC16(L)F707 FIGURE 3-6: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2 VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD): CASE 3 FIGURE 3-7: VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset 2010-2011 Microchip Technology Inc.
PIC16(L)F707 TABLE 3-5: INITIALIZATION CONDITION FOR REGISTERS Register W Address Power-on Reset/ Brown-out Reset(1) MCLR Reset/ WDT Reset Wake-up from Sleep through Interrupt/Time-out — xxxx xxxx uuuu uuuu uuuu uuuu INDF 00h/80h/ 100h/180h xxxx xxxx xxxx xxxx uuuu uuuu TMR0 01h/101h xxxx xxxx uuuu uuuu uuuu uuuu PCL 02h/82h/ 102h/182h 0000 0000 0000 0000 PC + 1(3) STATUS 03h/83h/ 103h/183h 0001 1xxx 000q quuu(4) uuuq quuu(4) FSR 04h/84h/ 104h/184h xxxx xxxx uuuu uuuu uuuu
PIC16(L)F707 TABLE 3-5: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED) Address Power-on Reset/ Brown-out Reset(1) MCLR Reset/ WDT Reset 1Fh --00 0000 --00 0000 --uu uuuu 81h/181h 1111 1111 1111 1111 uuuu uuuu 85h 1111 1111 1111 1111 uuuu uuuu TRISB 86h 1111 1111 1111 1111 uuuu uuuu TRISC 87h 1111 1111 1111 1111 uuuu uuuu TRISD 88h 1111 1111 1111 1111 uuuu uuuu TRISE 89h ---- 1111 ---- 1111 ---- uuuu PIE1 8Ch 0000 0000 0000 0000 uuuu uuuu PIE2 8Dh 0000 ---0 000
PIC16(L)F707 TABLE 3-5: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED) Address Power-on Reset/ Brown-out Reset(1) MCLR Reset/ WDT Reset 111h 0-00 0000 0-00 0000 u-uu uuuu TMRB 112h 0000 0000 0000 0000 uuuu uuuu DACCON0 113h 000- 00-- 000- 00-- uuu- uu-- DACCON1 114h ---0 0000 ---0 0000 ---u uuuu ANSELA 185h 1111 1111 1111 1111 uuuu uuuu ANSELB 186h 1111 1111 1111 1111 uuuu uuuu ANSELC 187h 1111 1111 1111 1111 uuuu uuuu ANSELD 188h 1111 1111 1111 1111 uuuu uuuu
PIC16(L)F707 4.0 INTERRUPTS The PIC16(L)F707 device family features an interruptible core, allowing certain events to preempt normal program flow. An Interrupt Service Routine (ISR) is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode.
PIC16(L)F707 4.1 Operation interrupts. Because the GIE bit is cleared, any interrupt that occurs while executing the ISR will be recorded through its interrupt flag, but will not cause the processor to redirect to the interrupt vector. Interrupts are disabled upon any device Reset.
PIC16(L)F707 4.3 Interrupts During Sleep Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate interrupt enable bit(s) set prior to entering Sleep. On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the SLEEP instruction.
PIC16(L)F707 4.5.1 INTCON REGISTER Note: The INTCON register is a readable and writable register, which contains the various enable and flag bits for TMR0 register overflow, PORTB change and external RB0/INT/SEG0 pin interrupts. REGISTER 4-1: R/W-0 INTCON: INTERRUPT CONTROL REGISTER R/W-0 GIE Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE of the INTCON register.
PIC16(L)F707 4.5.2 PIE1 REGISTER The PIE1 register contains the interrupt enable bits, as shown in Register 4-2. REGISTER 4-2: Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.
PIC16(L)F707 4.5.3 PIE2 REGISTER The PIE2 register contains the interrupt enable bits, as shown in Register 4-3. REGISTER 4-3: Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.
PIC16(L)F707 4.5.4 PIR1 REGISTER The PIR1 register contains the interrupt flag bits, as shown in Register 4-4. REGISTER 4-4: Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC16(L)F707 4.5.5 PIR2 REGISTER The PIR2 register contains the interrupt flag bits, as shown in Register 4-5. REGISTER 4-5: Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC16(L)F707 TABLE 4-1: Name INTCON OPTION_REG SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000x PSA PS2 PS1 PS0 1111 1111 1111 1111 PIE1 TMR1GIE RBPU INTEDG TMR0CS TMR0SE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 PIE2 TMR3GIE TMR3IE TMRBIE TMRAIE — — — CCP2IE 0000 ---0 0000 ---0 PIR1 TM
PIC16(L)F707 NOTES: DS41418B-page 50 2010-2011 Microchip Technology Inc.
PIC16(L)F707 5.0 LOW DROPOUT (LDO) VOLTAGE REGULATOR On power-up, the external capacitor will load the LDO voltage regulator. To prevent erroneous operation, the device is held in Reset while a constant current source charges the external capacitor. After the cap is fully charged, the device is released from Reset. For more information on recommended capacitor values and the constant current rate, refer to the LDO Regulator Characteristics Table in Section 25.0 “Electrical Specifications”.
PIC16(L)F707 NOTES: DS41418B-page 52 2010-2011 Microchip Technology Inc.
PIC16(L)F707 6.0 I/O PORTS FIGURE 6-1: There are thirty-five general purpose I/O pins available. Depending on which peripherals are enabled, some or all of the pins may not be available as general purpose I/O. In general, when a peripheral is enabled, the associated pin may not be used as a general purpose I/O pin. GENERIC I/O PORT OPERATION TRISx D Each port has two registers for its operation.
PIC16(L)F707 6.2 PORTA and TRISA Registers TRISA register are maintained set when using them as analog inputs. I/O pins configured as analog input always read ‘0’. PORTA is a 8-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register 6-3). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e.
PIC16(L)F707 6.2.1 ANSELA REGISTER The ANSELA register (Register 6-4) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELA bit high will cause all digital reads on the pin to be read as ‘0’ and allow analog functions on the pin to operate correctly. The state of the ANSELA bits has no affect on digital output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode will be analog.
PIC16(L)F707 6.2.2.4 RA3/AN3/VREF+/CPSA2 6.2.2.7 RA6/CPSB1/OSC2/CLKOUT/VCAP The RA3 pin is configurable to function as one of the following: The RA6 pin is configurable to function as one of the following: • • • • • • • • General purpose I/O Analog input for the A/D Voltage Reference input for the A/D Capacitive sensing input 6.2.2.
PIC16(L)F707 6.3 PORTB and TRISB Registers PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB (Register 6-6). Setting a TRISB bit (=1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). Example 6-2 shows how to initialize PORTB.
PIC16(L)F707 REGISTER 6-5: PORTB: PORTB REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown RB<7:0>: PORTB I/O Pin bit 1 = Port pin is > VIH 0 = Port pin is < VIL REGISTER 6-6: TRISB: PORTB TRI-STATE REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TRISB7
PIC16(L)F707 REGISTER 6-8: IOCB: INTERRUPT-ON-CHANGE PORTB REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IOCB7 IOCB6 IOCB5 IOCB4 IOCB3 IOCB2 IOCB1 IOCB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown IOCB<7:0>: Interrupt-on-Change PORTB Control bits 1 = Interrupt-on-change enabled 0 = Interrupt-on-change disabled REGISTER 6-9: ANSELB: PORTB ANA
PIC16(L)F707 6.3.4.4 RB3/AN9/CPSB11/CCP2 6.3.4.6 RB5/AN13/CPSB13/T1G/T3CKI These pins are configurable to function as one of the following: These pins are configurable to function as one of the following: • • • • • • • • • General purpose I/O Analog input for the ADC Capacitive sensing input Capture 2 input, Compare 2 output, and PWM2 output Note: CCP2 pin location may be selected as RB3 or RC1. 6.3.4.
PIC16(L)F707 6.4 EXAMPLE 6-3: PORTC and TRISC Registers PORTC is a 8-bit wide, bidirectional port. The corresponding data direction register is TRISC (Register 6-11). Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin).
PIC16(L)F707 6.4.1 ANSELC REGISTER The ANSELC register (Register 6-12) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELC bit high will cause all digital reads on the pin to be read as ‘0’ and allow analog functions on the pin to operate correctly. The state of the ANSELC bits has no affect on digital output functions. A pin with TRIS clear and ANSELC set will still operate as a digital output, but the Input mode will be analog.
PIC16(L)F707 6.4.2.3 RC2/CCP1/CPSB4/TBCKI 6.4.2.6 RC5/SDO/CPSA9 These pins are configurable to function as one of the following: These pins are configurable to function as one of the following: • General purpose I/O • Capture 1 input, Compare 1 output, and PWM1 output • Capacitive sensing input • TimerB Clock input • General purpose I/O • SPI data output • Capacitive sensing input 6.4.2.4 6.4.2.
PIC16(L)F707 6.5 EXAMPLE 6-4: PORTD and TRISD Registers BANKSEL CLRF BANKSEL CLRF BANKSEL MOVLW MOVWF PORTD is a 8-bit wide, bidirectional port. The corresponding data direction register is TRISD (Register 6-14). Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i.e.
PIC16(L)F707 REGISTER 6-14: TRISD: PORTD TRI-STATE REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown TRISD<7:0>: PORTD Tri-State Control bits 1 = PORTD pin configured as an input (tri-stated) 0 = PORTD pin configured as an output REGISTER 6-15: AN
PIC16(L)F707 6.5.2.6 RD5/CPSA13 6.5.2.8 RD7/CPSA15 These pins are configurable to function as one of the following: These pins are configurable to function as one of the following: • General purpose I/O • Capacitive sensing input • General purpose I/O • Capacitive sensing input 6.5.2.
PIC16(L)F707 6.6 EXAMPLE 6-5: PORTE and TRISE Registers PORTE is a 4-bit wide, bidirectional port. The corresponding data direction register is TRISE. Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISE bit (= 0) will make the corresponding PORTE pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin).
PIC16(L)F707 REGISTER 6-17: U-0 TRISE: PORTE TRI-STATE REGISTER U-0 — U-0 — — U-0 R-1 R/W-1 R/W-1 R/W-1 — TRISE3 TRISE2 TRISE1 TRISE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3 TRISE3: RE3 Port Tri-state Control bit This bit is always ‘1’ as RE3 is an input only bit 2-0 TRISE<2:0>: RE<2:0> Tri-State Control bits(1) 1 = PORTE pin configure
PIC16(L)F707 6.6.2.
PIC16(L)F707 NOTES: DS41418B-page 70 2010-2011 Microchip Technology Inc.
PIC16(L)F707 7.0 OSCILLATOR MODULE 7.1 Overview Clock source modes are configured by the FOSC bits in Configuration Word 1 (CONFIG1). The oscillator module can be configured for one of eight modes of operation. The oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 7-1 illustrates a block diagram of the oscillator module. 1. 2. 3.
PIC16(L)F707 7.2 Clock Source Modes Clock source modes can be classified as external or internal. • Internal clock source (INTOSC) is contained within the oscillator module and derived from a 500 kHz high precision oscillator. The oscillator module has eight selectable output frequencies, with a maximum internal frequency of 16 MHz. • External clock modes rely on external circuitry for the clock source.
PIC16(L)F707 7.4 Oscillator Control The Oscillator Control (OSCCON) register (Figure 7-1) displays the status and allows frequency selection of the internal oscillator (INTOSC) system clock.
PIC16(L)F707 7.5 Oscillator Tuning The INTOSC is factory calibrated but can be adjusted in software by writing to the OSCTUNE register (Register 7-2). When the OSCTUNE register is modified, the INTOSC frequency will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred. The default value of the OSCTUNE register is ‘0’. The value is a 6-bit two’s complement number.
PIC16(L)F707 7.6 External Clock Modes 7.6.1 OSCILLATOR START-UP TIMER (OST) If the oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) counts 1024 oscillations on the OSC1 pin before the device is released from Reset. This occurs following a Power-on Reset (POR) and when the Power-up Timer (PWRT) has expired (if configured), or a wake-up from Sleep. During this time, the program counter does not increment and program execution is suspended.
PIC16(L)F707 FIGURE 7-4: CERAMIC RESONATOR OPERATION (XT OR HS MODE) FIGURE 7-5: EXTERNAL RC MODES VDD PIC® MCU REXT PIC® MCU OSC1/CLKIN Internal Clock OSC1/CLKIN CEXT C1 To Internal Logic RP(3) C2 Ceramic RS(1) Resonator RF(2) VSS Sleep FOSC/4 or I/O(2) OSC2/CLKOUT Recommended values: 10 k REXT 100 k, <3V 3 k REXT 100 k, 3-5V CEXT > 20 pF, 2-5V Note 1: A series resistor (RS) may be required for ceramic resonators with low drive level.
PIC16(L)F707 8.0 DEVICE CONFIGURATION 8.1 There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 register at 2007h and Configuration Word 2 register at 2008h. These registers are only accessible during programming. Device Configuration consists of Configuration Word 1 and Configuration Word 2 registers, Code Protection and Device ID.
PIC16(L)F707 REGISTER 8-1: bit 2-0 CONFIG1: CONFIGURATION WORD REGISTER 1 (CONTINUED) FOSC<2:0>: Oscillator Selection bits 111 = RC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, RC on RA7/OSC1/CLKIN 110 = RCIO oscillator: I/O function on RA6/OSC2/CLKOUT pin, RC on RA7/OSC1/CLKIN 101 = INTOSC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN 100 = INTOSCIO oscillator: I/O function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN 011 = EC: I/O function on RA6/OSC
PIC16(L)F707 8.2 Code Protection If the code protection bit(s) have not been programmed, the on-chip program memory can be read out using ICSP™ for verification purposes. Note: 8.3 The entire Flash program memory will be erased when the code protection is turned off. See the “PIC16F707/PIC16LF707 Memory Programming Specification” (DS41332) for more information.
PIC16(L)F707 NOTES: DS41418B-page 80 2010-2011 Microchip Technology Inc.
PIC16(L)F707 9.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 8-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a 8-bit binary result via successive approximation and stores the conversion result into the ADC result register (ADRES).
PIC16(L)F707 9.1 9.1.3 ADC Configuration The ADREF bits of the ADCON1 register provides control of the positive voltage reference. The positive voltage reference can be either VDD, an external voltage source or the internal Fixed Voltage Reference. The negative voltage reference is always connected to the ground reference. See Section 10.0 “Fixed Voltage Reference” for more details on the Fixed Voltage Reference.
PIC16(L)F707 FIGURE 9-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES Tcy to TAD TAD0 TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 b7 b6 b5 b4 b3 b2 b1 b0 Conversion Starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO/DONE bit 9.1.
PIC16(L)F707 9.2 9.2.1 ADC Operation STARTING A CONVERSION To enable the ADC module, the ADON bit of the ADCON0 register must be set to a ‘1’. Setting the GO/ DONE bit of the ADCON0 register to a ‘1’ will start the Analog-to-Digital conversion. Note: The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section 9.2.6 “A/D Conversion Procedure”. 9.2.5 The Special Event Trigger of the CCP module allows periodic ADC measurements without software intervention.
PIC16(L)F707 EXAMPLE 9-1: A/D CONVERSION ;This code block configures the ADC ;for polling, Vdd reference, Frc clock ;and AN0 input. ; ;Conversion start & polling for completion ; are included.
PIC16(L)F707 9.2.7 ADC REGISTER DEFINITIONS The following registers are used to control the operation of the ADC.
PIC16(L)F707 REGISTER 9-2: ADCON1: A/D CONTROL REGISTER 1 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 — ADCS2 ADCS1 ADCS0 — — ADREF1 ADREF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 011 = FRC (clock supplied from a dedicated RC oscillator) 100 = FOSC/4 101
PIC16(L)F707 9.3 A/D Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 9-3. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), refer to Figure 9-3.
PIC16(L)F707 FIGURE 9-3: ANALOG INPUT MODEL VDD Rs VA VT 0.6V ANx CPIN 5 pF VT 0.6V RIC 1k Sampling Switch SS Rss I LEAKAGE(1) CHOLD = 10 pF VSS/VREF- Legend: CHOLD CPIN = Sample/Hold Capacitance = Input Capacitance 6V 5V VDD 4V 3V 2V I LEAKAGE = Leakage current at the pin due to various junctions = Interconnect Resistance RIC RSS = Resistance of Sampling Switch SS = Sampling Switch VT = Threshold Voltage RSS 5 6 7 8 9 10 11 Sampling Switch (k) Note 1: Refer to Section 25.
PIC16(L)F707 TABLE 9-2: Name SUMMARY OF ASSOCIATED ADC REGISTERS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 --00 0000 ADCON1 — ADCS2 ADCS1 ADCS0 — — ADREF1 ADREF0 -000 --00 -000 --00 ANSELA ANSA7 ANSA6 ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 1111 1111 1111 1111 ANSELB ANSB7 ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 1111 1111 1111 1111 ANSELE — — — — —
PIC16(L)F707 10.0 FIXED VOLTAGE REFERENCE 10.1 Independent Gain Amplifiers The Fixed Voltage Reference, or FVR, is a stable voltage reference independent of VDD with 1.024V, 2.048V or 4.096V selectable output levels. The output of the FVR can be configured to supply a reference voltage to the following: The output of the FVR supplied to the ADC and CSM/DAC modules is routed through the two independent programmable gain amplifiers.
PIC16(L)F707 REGISTER 10-1: FVRCON: FIXED VOLTAGE REFERENCE REGISTER R-q R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 FVRRDY(1) FVREN — — CDAFVR1(2) CDAFVR0(2) ADFVR1(2) ADFVR0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown q = Value depends on condition bit 7 FVRRDY: Fixed Voltage Reference Ready Flag bit(1) 0 = Fixed Voltage Reference output is not
PIC16(L)F707 11.0 DIGITAL-TO-ANALOG CONVERTER (DAC) MODULE The Digital-to-Analog Converter supplies a variable voltage reference, ratiometric with VDD, with 32 selectable output levels. The output of the DAC can be configured to supply a reference voltage to the following: 11.1 Output Voltage Selection The DAC has 32 voltage level ranges. The 32 levels are set with the DACR<4:0> bits of the DACCON1 register.
PIC16(L)F707 FIGURE 11-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM DACEN DACLPS VDD VREF DACPSS[1:0] = 00 DACPSS[1:0] = 01 DACPSS[1:0] = 10 FVR BUFFER 2 DACR<4:0> R R R R R EXAMPLE 11-1: DACEN R DACLPS R (To Capacitive Sensing Module) 16-to-1 MUX R 32 Steps DAC DACOE DACOUT pin VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC16F707/ PIC16LF707 DAC Module R Voltage Reference Output Impedance DS41418B-page 94 DACOUT + – Buffered DAC Output 2010-2011 Microchip Technology Inc.
PIC16(L)F707 REGISTER 11-1: DACCON0: VOLTAGE REFERENCE CONTROL REGISTER 0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 U-0 U-0 DACEN DACLPS DACOE — DACPSS1 DACPSS0 — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 DACEN: Digital-to-Analog Converter Enable bit 0 = Digital
PIC16(L)F707 TABLE 11-1: Name FVRCON DACCON0 DACCON1 Legend: REGISTERS ASSOCIATED WITH THE DIGITAL-TO-ANALOG CONVERTER Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 FVRRDY FVREN Reserved Reserved DACEN DACLPS DACOE — — — — DACR4 DACR3 Value on POR, BOR Value on all other Resets Bit 2 Bit 1 Bit 0 CDAFVR1 CDAFVR0 ADFVR1 ADFVR0 q000 0000 q000 0000 DACPSS1 DACPSS0 — — 000- 00-- 000- 00-- DACR2 DACR1 DACR0 ---0 0000 ---0 0000 — = Unimplemented locations, read as ‘0’.
PIC16(L)F707 12.0 TIMER0 MODULE The Timer0 module is an 8-bit timer/counter with the following features: • • • • • 8-bit timer/counter register (TMR0) 8-bit prescaler (shared with Watchdog Timer) Programmable internal or external clock source Programmable external clock edge selection Interrupt on overflow Figure 12-1 is a block diagram of the Timer0 module.
PIC16(L)F707 12.1 Timer0 Operation The Timer0 module can be used as either an 8-bit timer or an 8-bit counter. 12.1.1 8-BIT TIMER MODE The Timer0 module will increment every instruction cycle, if used without a prescaler. 8-bit Timer mode is selected by clearing the TMR0CS bit of the OPTION register. When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. Note: 12.1.
PIC16(L)F707 REGISTER 12-1: OPTION_REG: OPTION REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG TMR0CS TMR0SE PSA PS2 PS1 PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual PORT latch values bit 6 INTEDG: Interrupt Edge Select bit
PIC16(L)F707 NOTES: DS41418B-page 100 2010-2011 Microchip Technology Inc.
PIC16(L)F707 13.
PIC16(L)F707 FIGURE 13-1: TIMER1/TIMER3 BLOCK DIAGRAM TxGSS<1:0> TxG 00 From TimerA/B Overflow(4) 01 TxGSPM 0 TxG_IN TxGVAL 0 From Timer2 Match PR2 10 From WDT Overflow 11 D Q CK R Q Single Pulse Acq. Control 1 1 Q1 D RD TXGCON EN Interrupt TxGGO/DONE Data Bus Q det Set TMRxGIF TxGPOL TMRxGE TxGTM Set flag bit TMRxIF on Overflow TMRxON TMRx(2) TMRxH EN TxCLK TMRxL Q Synchronized clock input 0 D 1 TMRxCS<1:0> Sense(5) T1OSO/T1CKI OUT Cap.
PIC16(L)F707 13.1 Timer1/3 Operation 13.2 The Timer1 and Timer3 modules are 16-bit incrementing counters which are accessed through the TMRxH:TMRxL register pair. Writes to TMRxH or TMRxL directly update the counter. When used with an internal clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module can be used as either a timer or counter and increments on every selected edge of the external source.
PIC16(L)F707 13.3 Timer1/3 Prescaler Timer1 and Timer3 have four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The TxCKPS bits of the TxCON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMRxH or TMRxL. 13.4 Timer1/3 Oscillator 13.5.
PIC16(L)F707 TABLE 13-5: TxGSS TIMER1/3 GATE SOURCES Timer1 Gate Source Timer3 Gate Source 00 Timer1 Gate Pin Timer3 Gate Pin 01 Overflow of TimerA (TMRA increments from FFh to 00h) Overflow of TimerB (TMRB increments from FFh to 00h) 10 Timer2 match PR2 (TMR2 increments to match PR2) Timer2 match PR2 (TMR2 increments to match PR2) 11 Count Enabled by WDT Overflow (Watchdog Time-out interval expired) Count Enabled by WDT Overflow (Watchdog Time-out interval expired) 13.6.
PIC16(L)F707 13.6.7 TIMER1/3 GATE TOGGLE MODE When Timer1/3 Gate Toggle mode is enabled, it is possible to measure the full-cycle length of a Timer1/3 gate signal, as opposed to the duration of a single level pulse. The Timer1/3 gate source is routed through a flip-flop that changes state on every incrementing edge of the signal. See Figure 13-4 for timing details. Timer1/3 Gate Toggle mode is enabled by setting the TxGTM bit of the TxGCON register.
PIC16(L)F707 13.8 Timer1/3 Operation During Sleep Timer1/3 can only operate during Sleep when setup in Asynchronous Counter mode. In this mode, an external crystal or clock source can be used to increment the counter.
PIC16(L)F707 FIGURE 13-3: TIMER1/TIMER3 GATE COUNT ENABLE MODE TMRxGE TxGPOL TxG_IN TxCKI TxGVAL Timer1/3 N FIGURE 13-4: N+1 N+2 N+3 N+4 TIMER1/TIMER3 GATE TOGGLE MODE TMRxGE TxGPOL TxGTM TxG_IN TxCKI TxGVAL TIMER1/3 DS41418B-page 108 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 2010-2011 Microchip Technology Inc.
PIC16(L)F707 FIGURE 13-5: TIMER1/TIMER3 GATE SINGLE-PULSE MODE TMRxGE TxGPOL TxGSPM TxGGO/ Cleared by hardware on falling edge of TxGVAL Set by software DONE Counting enabled on rising edge of TxG TxG_IN TxCKI TxGVAL TIMER1/3 TMRxGIF N Cleared by software 2010-2011 Microchip Technology Inc.
PIC16(L)F707 FIGURE 13-6: TIMER1/TIMER3 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMRxGE TxGPOL TxGSPM TxGTM TxGGO/ Cleared by hardware on falling edge of TxGVAL Set by software DONE Counting enabled on rising edge of TxG TxG_IN TxCKI TxGVAL TIMER1/3 TMRxGIF DS41418B-page 110 N Cleared by software N+1 N+2 N+3 Set by hardware on falling edge of TxGVAL N+4 Cleared by software 2010-2011 Microchip Technology Inc.
PIC16(L)F707 13.11 Timer1/3 Control Register The Timer1/3 Control register (TxCON), shown in Register 13-1, is used to control Timer1/3 and select the various features of the Timer1/3 module.
PIC16(L)F707 REGISTER 13-2: TxGCON: TIMER1/TIMER3 GATE CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 R/W-0/0 R/W-0/0 TMRxGE TxGPOL TxGTM TxGSPM TxGGO/ DONE TxGVAL TxGSS1 TxGSS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 TMRxGE: Timerx Gate Enable bi
PIC16(L)F707 14.0 TIMERA/B MODULES TimerA and TimerB are two more Timer0-type modules. Timers A and B are available as generalpurpose timers/counters, and are closely integrated with the capacitive sensing modules.
PIC16(L)F707 14.1 14.1.3 TimerA/B Operation The TimerA/B modules can be used as either 8-bit timers or 8-bit counters. Additionally, the modules can also be used to set Timer1’s/Timer3’s period of measurement for the capacitive sensing modules via Timer1’s or Timer3’s gate feature. TABLE 14-1: CPSOSC/TIMER ASSOCIATION Cap Sense Oscillator Divider Timer Period Measurement CPS A TimerA Timer1 CPS B TimerB Timer3 14.1.
PIC16(L)F707 REGISTER 14-1: TxCON: TIMERA/TIMERB CONTROL REGISTER R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TMRxON — TMRxCS TMRxSE TMRxPSA TMRxPS2 TMRxPS1 TMRxPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TMRxON: TimerA/TimerB On/Off Control bit 1 = Timerx is enabled 0 = Timerx is disabled bit 6 Unimplemented: Read as ‘0’ bit 5 TMRx
PIC16(L)F707 NOTES: DS41418B-page 116 2010-2011 Microchip Technology Inc.
PIC16(L)F707 15.0 TIMER2 MODULE The Timer2 module is an 8-bit timer with the following features: • • • • • 8-bit timer register (TMR2) 8-bit period register (PR2) Interrupt on TMR2 match with PR2 Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) Timer2 is turned on by setting the TMR2ON bit in the T2CON register to a ‘1’. Timer2 is turned off by clearing the TMR2ON bit to a ‘0’. The Timer2 prescaler is controlled by the T2CKPS bits in the T2CON register.
PIC16(L)F707 REGISTER 15-1: T2CON: TIMER2 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS<3:0>: Timer2 Output Postscaler Select bits 0000 = 1:1 Postscaler 0001 = 1:2 Postscaler 0010 = 1:3 Postscaler 0011 = 1:4 Postscal
PIC16(L)F707 16.0 CAPACITIVE SENSING MODULE The capacitive sensing modules (CSM) allow for an interaction with an end user without a mechanical interface. In a typical application, the capacitive sensing module is attached to a pad on a Printed Circuit Board (PCB), which is electrically isolated from the end user. When the end user places their finger over the PCB pad, a capacitive load is added, causing a frequency shift in the capacitive sensing module.
PIC16(L)F707 FIGURE 16-1: CAPACITIVE SENSING BLOCK DIAGRAM TimerA/B Module Set TMRxIF TMRxCS CPSxCH<3:0> CPSxON(1) TxXCS FOSC/4 CPSx0 TxCKI 0 TMRx 0 Overflow 1 CPSx1 1 CPSx2 CPSx3 CPSxRNG<1:0> CPSx4 CPSxON CPSx5 CPSx6 CPSx8 Capacitive Sensing Oscillator CPSx9 CPSxOSC CPSx7 Timer1/3 Module TMRxCS<1:0> FOSC CPSx10 FOSC/4 CPSx11 Int. Ref.
PIC16(L)F707 FIGURE 16-2: CAPACITIVE SENSING OSCILLATOR BLOCK DIAGRAM Oscillator Module VDD (1) + (2) - S CPSx (1) Analog Pin - (2) Q CPSxCLK R + Internal References 0 0 Ref- Ref+ 1 DAC(3) 1 FVR(3) CPSxRM Note 1: 2: Module Enable and Power mode selections are not shown. Comparators remain active in Noise Detection mode. 2010-2011 Microchip Technology Inc.
PIC16(L)F707 16.1 Analog MUX Each capacitive sensing module can monitor up to 16 inputs, providing 32 capacitive sensing inputs in total. The capacitive sensing inputs are defined as CPSA<15:0> for capacitive sensing module A, and CPSB<15:0> for capacitive sensing module B. To determine if a frequency change has occurred the use must: • Select the appropriate CPS pin by setting the CPSxCH<3:0> bits of the CPSxCON1 register. • Set the corresponding ANSEL bit. • Set the corresponding TRIS bit.
PIC16(L)F707 16.4 Power Modes The capacitive sensing oscillator can operate in one of seven different power modes. The power modes are separated into two ranges; the low range and the high range. When the oscillator's low range is selected, the fixed internal voltage references of the capacitive sensing oscillator are being used. When the oscillator's high range is selected, the variable voltage references supplied by the FVR and DAC modules are being used.
PIC16(L)F707 16.6.1 TIMERA/B 16.7 To select TimerA/B as the timer resource for the capacitive sensing module: • Set the TAXCS/TBXCS bit of the CPSACON0/ CPSBCON0 register. • Clear the TMRACS/TMRBCS bit of the TACON/ TBCON register. When TimerA/B is chosen as the timer resource, the capacitive sensing oscillator will be the clock source for TimerA/B. Refer to Section 14.0 “TimerA/B Modules” for additional information. 16.6.
PIC16(L)F707 16.7.3 FREQUENCY THRESHOLD The frequency threshold should be placed midway between the value of nominal frequency and the reduced frequency of the capacitive sensing oscillator. Refer to Application Note AN1103, “Software Handling for Capacitive Sensing” (DS01103) for more detailed information on the software required for capacitive sensing module. Note: For more information on general capacitive sensing refer to Application Notes: 16.
PIC16(L)F707 REGISTER 16-1: CPSxCON0: CAPACITIVE SENSING CONTROL REGISTER 0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 R-0/0 R/W-0/0 CPSxON CPSxRM — — CPSxRNG1 CPSxRNG0 CPSxOUT TxXCS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CPSxON: Capacitive Sensing Module Enable bit 1 = Capacitive sensing module i
PIC16(L)F707 REGISTER 16-2: CPSxCON1: CAPACITIVE SENSING CONTROL REGISTER 1 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — — — CPSxCH3 CPSxCH2 CPSxCH1 CPSxCH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 CPSxCH<3:0>: Capacitive Sensing Channel Select bits I
PIC16(L)F707 TABLE 16-4: SUMMARY OF REGISTERS ASSOCIATED WITH CAPACITIVE SENSING Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets ANSELA ANSA7 ANSA6 ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 1111 1111 1111 1111 ANSELB ANSB7 ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 1111 1111 1111 1111 ANSELC ANSC7 ANSC6 ANSC5 — — ANSC2 ANSC1 ANSC0 111- -111 111- -111 ANSELD ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1 ANSD0 1111 1111 111
PIC16(L)F707 17.0 CAPTURE/COMPARE/PWM (CCP) MODULE The Capture/Compare/PWM module is a peripheral which allows the user to time and control different events. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate a pulse-width modulated signal of varying frequency and duty cycle.
PIC16(L)F707 REGISTER 17-1: CCPxCON: CCPx CONTROL REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DCxB<1:0>: PWM Duty Cycle Least Significant bits Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs
PIC16(L)F707 17.1 17.1.3 Capture Mode In Capture mode, CCPRxH:CCPRxL captures the 16-bit value of the TMR1 register when an event occurs on pin CCPx. An event is defined as one of the following and is configured by the CCPxM<3:0> bits of the CCPxCON register: • • • • Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge 17.1.1 CCPx PIN CONFIGURATION In Capture mode, the CCPx pin should be configured as an input by setting the associated TRIS control bit.
PIC16(L)F707 TABLE 17-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets ANSELB ANSB7 ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 1111 1111 1111 1111 ANSELC ANSC7 ANSC6 ANSC5 — — ANSC2 ANSC1 ANSC0 111- -111 111- -111 APFCON — — — — — — SSSEL CCP2SEL ---- --00 ---- --00 CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 CCP2CON — — DC2B1 D
PIC16(L)F707 17.2 17.2.2 Compare Mode In Compare mode, the 16-bit CCPRx register value is constantly compared against the TMR1 register pair value. When a match occurs, the CCPx module may: • • • • • Toggle the CCPx output Set the CCPx output Clear the CCPx output Generate a Special Event Trigger Generate a Software Interrupt In Compare mode, Timer1 must be running in either Timer mode or Synchronized Counter mode. The compare operation may not work in Asynchronous Counter mode.
PIC16(L)F707 TABLE 17-4: Name SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets --00 0000 ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON --00 0000 ANSELB ANSB7 ANSB6 ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 1111 1111 1111 1111 ANSELC ANSC7 ANSC6 ANSC5 — — ANSC2 ANSC1 ANSC0 111- -111 111- -111 APFCON — — — — — — SSSEL CCP2SEL ---- --00 ---- --00 CCP1CON — — DC1B1 DC1B0 CCP
PIC16(L)F707 17.3 PWM Mode The PWM mode generates a pulse-width modulated signal on the CCPx pin. The duty cycle, period and resolution are determined by the following registers: • • • • The PWM output (Figure 17-4) has a time base (period) and a time that the output stays high (duty cycle). FIGURE 17-4: PR2 T2CON CCPRxL CCPxCON CCP PWM OUTPUT Period Pulse Width In Pulse-Width Modulation (PWM) mode, the CCP module produces up to a 10-bit resolution PWM output on the CCPx pin.
PIC16(L)F707 17.3.2 PWM PERIOD EQUATION 17-2: PULSE WIDTH The PWM period is specified by the PR2 register of Timer2. The PWM period can be calculated using the formula of Equation 17-1. Pulse Width = CCPRxL:CCPxCON<5:4> EQUATION 17-1: Note: TOSC = 1/FOSC PWM PERIOD PWM Period = PR2 + 1 4 T OSC (TMR2 Prescale Value) Note: TOSC = 1/FOSC When TMR2 is equal to PR2, the following three events occur on the next increment cycle: • TMR2 is cleared • The CCPx pin is set.
PIC16(L)F707 17.3.4 PWM RESOLUTION EQUATION 17-4: The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. log 4 PR2 + 1 Resolution = ------------------------------------------ bits log 2 The maximum PWM resolution is 10 bits when PR2 is 255. The resolution is a function of the PR2 register value as shown by Equation 17-4.
PIC16(L)F707 6. Enable PWM output pin: • Wait until Timer2 overflows, TMR2IF bit of the PIR1 register is set. See the Note below. • Enable the PWM pin (CCPx) output driver(s) by clearing the associated TRIS bit(s). Note: In order to send a complete duty cycle and period on the first PWM output, the above steps must be included in the setup sequence. If it is not critical to start with a complete PWM signal on the first output, then step 6 may be ignored.
PIC16(L)F707 18.0 ADDRESSABLE UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (AUSART) The AUSART module includes the following capabilities: • • • • • • • • • • The Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART) module is a serial I/O communications peripheral. It contains all the clock generators, shift registers and data buffers necessary to perform an input or output serial data transfer independent of device program execution.
PIC16(L)F707 FIGURE 18-2: AUSART RECEIVE BLOCK DIAGRAM SPEN CREN RX/DT Baud Rate Generator +1 SPBRG RSR Register MSb Pin Buffer and Control Data Recovery FOSC Multiplier x4 x16 x64 SYNC 1 0 0 BRGH x 1 0 Stop OERR (8) ••• 7 1 LSb 0 START RX9 ÷n n FERR RX9D RCREG Register FIFO 8 Data Bus RCIF RCIE Interrupt The operation of the AUSART module is controlled through two registers: • Transmit Status and Control (TXSTA) • Receive Status and Control (RCSTA) These registers are d
PIC16(L)F707 18.1 AUSART Asynchronous Mode The AUSART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is implemented with two levels: a VOH mark state which represents a ‘1’ data bit, and a VOL space state which represents a ‘0’ data bit. NRZ refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission.
PIC16(L)F707 18.1.1.4 TSR Status 18.1.1.6 The TRMT bit of the TXSTA register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXREG. The TRMT bit remains clear until all bits have been shifted out of the TSR register. No interrupt logic is tied to this bit, so the user has to poll this bit to determine the TSR status. Note: 1. 2. 3.
PIC16(L)F707 FIGURE 18-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXREG Word 2 Word 1 BRG Output (Shift Clock) TX/CK pin Start bit TXIF bit (Transmit Buffer Empty Flag) bit 0 bit 1 Word 1 1 TCY bit 7/8 Stop bit Start bit bit 0 Word 2 1 TCY TRMT bit (Transmit Shift Reg. Empty Flag) Note: Word 2 Transmit Shift Reg. This timing diagram shows two consecutive transmissions. TABLE 18-1: Name Word 1 Transmit Shift Reg.
PIC16(L)F707 18.1.2.3 Note 1: When the SPEN bit is set, the TX/CK I/O pin is automatically configured as an output, regardless of the state of the corresponding TRIS bit and whether or not the AUSART transmitter is enabled. The PORT latch is disconnected from the output driver so it is not possible to use the TX/CK pin as a general purpose output. 2: The corresponding ANSEL bit must be cleared for the RX/DT port pin to ensure proper AUSART functionality. 18.1.2.
PIC16(L)F707 18.1.2.6 Receiving 9-bit Characters The AUSART supports 9-bit character reception. When the RX9 bit of the RCSTA register is set the AUSART will shift 9 bits into the RSR for each character received. The RX9D bit of the RCSTA register is the ninth and Most Significant data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the 8 Least Significant bits from the RCREG. 18.1.2.
PIC16(L)F707 FIGURE 18-5: ASYNCHRONOUS RECEPTION Start bit bit 0 RX/DT pin bit 7/8 Stop bit bit 1 Rcv Shift Reg Rcv Buffer Reg Start bit bit 0 bit 7/8 Stop bit Start bit bit 7/8 Stop bit Word 2 RCREG Word 1 RCREG Read Rcv Buffer Reg RCREG RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set.
PIC16(L)F707 REGISTER 18-1: R/W-0 CSRC TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0 TX9 TXEN(1) SYNC — BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6
PIC16(L)F707 REGISTER 18-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit(1) 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset) bit 6 RX
PIC16(L)F707 18.2 EXAMPLE 18-1: AUSART Baud Rate Generator (BRG) CALCULATING BAUD RATE ERROR For a device with FOSC of 16 MHz, desired baud rate of 9600, and Asynchronous mode with SYNC = 0 and BRGH = 0 (as seen in Table 18-5): The Baud Rate Generator (BRG) is an 8-bit timer that is dedicated to the support of both the asynchronous and synchronous AUSART operation.
PIC16(L)F707 TABLE 18-5: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0 BAUD RATE FOSC = 20.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 18.432 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 16.0000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) 300 — — — — — — — — — — — — 1200 1221 1.73 255 1200 0.00 239 1201 0.08 207 1200 0.00 143 2400 2404 0.16 129 2400 0.00 119 2403 0.
PIC16(L)F707 TABLE 18-5: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 1 BAUD RATE FOSC = 8.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 4.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 3.6864 MHz Actual Rate FOSC = 1.000 MHz % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 300 1200 — — — — — — — 1202 — 0.16 — 207 — 1200 — 0.00 — 191 300 1202 0.16 0.16 207 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.
PIC16(L)F707 18.3 AUSART Synchronous Mode Synchronous serial communications are typically used in systems with a single master and one or more slaves. The master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. There are two signal lines in Synchronous mode: a bidirectional data line and a clock line.
PIC16(L)F707 FIGURE 18-6: SYNCHRONOUS TRANSMISSION RX/DT pin bit 0 bit 1 Word 1 bit 2 bit 7 bit 0 bit 1 Word 2 bit 7 TX/CK pin Write to TXREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit TXEN bit Note: ‘1’ ‘1’ Synchronous Master mode, SPBRG = 0, continuous transmission of two 8-bit words.
PIC16(L)F707 18.3.1.4 Synchronous Master Reception Data is received at the RX/DT pin. The RX/DT pin output driver is automatically disabled when the AUSART is configured for synchronous master receive operation. In Synchronous mode, reception is enabled by setting either the Single Receive Enable bit (SREN of the RCSTA register) or the Continuous Receive Enable bit (CREN of the RCSTA register).
PIC16(L)F707 FIGURE 18-8: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TX/CK pin Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RCREG Note: Timing diagram demonstrates Synchronous Master mode with bit SREN = 1 and bit BRGH = 0.
PIC16(L)F707 18.3.2 SYNCHRONOUS SLAVE MODE If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: The following bits are used to configure the AUSART for synchronous slave operation: • • • • • 1. SYNC = 1 CSRC = 0 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 2. 3. 4. Setting the SYNC bit of the TXSTA register configures the device for synchronous operation.
PIC16(L)F707 18.3.2.3 AUSART Synchronous Slave Reception 18.3.2.4 The operation of the Synchronous Master and Slave modes is identical (Section 18.3.1.4 “Synchronous Master Reception”), with the following exceptions: 1. 2. • Sleep • CREN bit is always set, therefore the receiver is never Idle • SREN bit, which is a “don’t care” in Slave mode 3. 4. A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep.
PIC16(L)F707 18.4 AUSART Operation During Sleep The AUSART will remain active during Sleep only in the Synchronous Slave mode. All other modes require the system clock and therefore cannot generate the necessary signals to run the transmit or receive shift registers during Sleep. Synchronous Slave mode uses an externally generated clock to run the transmit and receive shift registers. 18.4.
PIC16(L)F707 19.0 SSP MODULE OVERVIEW The Synchronous Serial Port (SSP) module is a serial interface useful for communicating with other peripherals or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. The SSP module can operate in one of two modes: • Serial Peripheral Interface (SPI) • Inter-Integrated Circuit (I2C™) 19.1 A typical SPI connection between microcontroller devices is shown in Figure 19-1.
PIC16(L)F707 FIGURE 19-2: SPI MODE BLOCK DIAGRAM 19.1.1 Internal Data Bus Read In Master mode, data transfer can be initiated at any time because the master controls the SCK line. Master mode determines when the slave (Figure 19-1, Processor 2) transmits data via control of the SCK line. Write 19.1.1.
PIC16(L)F707 19.1.1.3 Master Mode Setup In Master mode, the data is transmitted/received as soon as the SSPBUF register is loaded with a byte value. If the master is only going to receive, SDO output could be disabled (programmed and used as an input). The SSPSR register will continue to shift in the signal present on the SDI pin at the programmed clock rate. When initializing SPI Master mode operation, several options need to be specified.
PIC16(L)F707 FIGURE 19-3: SPI MASTER MODE WAVEFORM Write to SSPBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) 4 Clock Modes SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO (CKE = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDO (CKE = 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 0 bit 7 Input Sample (SMP = 0) SDI (SMP = 1) bit 0 bit 7 Input Sample (SMP = 1) SSPIF SSPSR to SSPBUF EXAMPLE 19-1: LOOP BANKSEL BTFSS GOTO BANKSEL MOVF MOVWF MOVF MOVWF
PIC16(L)F707 19.1.2 SLAVE MODE For any SPI device acting as a slave, the data is transmitted and received as external clock pulses appear on the SCK pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. 19.1.2.1 Slave Mode Operation The SSP consists of a transmit/receive shift register (SSPSR) and a buffer register (SSPBUF). The SSPSR shifts the data in and out of the device, MSb first.
PIC16(L)F707 FIGURE 19-4: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 SDI (SMP = 0) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF FIGURE 19-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO SDI (SMP = 0) bit 6 bit 7 bit 7 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
PIC16(L)F707 19.1.2.4 Slave Select Operation The SS pin allows Synchronous Slave mode operation. The SPI must be in Slave mode with SS pin control enabled (SSPM<3:0> = 0100). The associated TRIS bit for the SS pin must be set, making SS an input. Note: In Slave Select mode, when: • SS = 0, The device operates as specified in Section 19.1.2 “Slave Mode”. • SS = 1, The SPI module is held in Reset and the SDO pin will be tri-stated.
PIC16(L)F707 REGISTER 19-1: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (SPI MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in sof
PIC16(L)F707 REGISTER 19-2: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (SPI MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SMP: SPI Data Input Sample Phase bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleare
PIC16(L)F707 TABLE 19-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets 1111 1111 ANSELA ANSA7 ANSA6 ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0 1111 1111 APFCON — — — — — — SSSEL CCP2SEL ---- --00 ---- --00 INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000x PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 PIR1 TMR1G
PIC16(L)F707 I2C Mode 19.2 FIGURE 19-8: The SSP module, in I2C mode, implements all slave functions, except general call support. It provides interrupts on Start and Stop bits in hardware to facilitate firmware implementations of the master functions. The SSP module implements the I2C Standard mode specifications: VDD Data is sampled on the rising edge and shifted out on the falling edge of the clock. This ensures that the SDA signal is valid during the SCL high time.
PIC16(L)F707 19.2.2 START AND STOP CONDITIONS During times of no data transfer (Idle time), both the clock line (SCL) and the data line (SDA) are pulled high through external pull-up resistors. The Start and Stop conditions determine the start and stop of data transmission. The Start condition is defined as a high-to-low transition of the SDA line while SCL is high. The Stop condition is defined as a low-to-high transition of the SDA line while SCL is high.
PIC16(L)F707 19.2.4 ADDRESSING Once the SSP module has been enabled, it waits for a Start condition to occur. Following the Start condition, the 8 bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock line (SCL). 19.2.4.1 7-bit Addressing In 7-bit Addressing mode (Figure 19-10), the value of register SSPSR<7:1> is compared to the value of register SSPADD<7:1>. The address is compared on the falling edge of the eighth clock (SCL) pulse.
PIC16(L)F707 19.2.5 RECEPTION When the R/W bit of the received address byte is clear, the master will write data to the slave. If an address match occurs, the received address is loaded into the SSPBUF register. An address byte overflow will occur if that loaded address is not read from the SSPBUF before the next complete byte is received. An SSP interrupt is generated for each data transfer byte. The BF, R/W and D/A bits of the SSPSTAT register are used to determine the status of the last received byte.
2010-2011 Microchip Technology Inc.
PIC16(L)F707 19.2.6 TRANSMISSION When the R/W bit of the received address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set and the slave will respond to the master by reading out data. After the address match, an ACK pulse is generated by the slave hardware and the SCL pin is held low (clock is automatically stretched) until the slave is ready to respond. See Section 19.2.7 “Clock Stretching”.
2010-2011 Microchip Technology Inc. CKP UA BF SSPIF 1 SCL S 1 2 1 4 1 5 0 6 7 A9 A8 UA is set indicating that the SSPADD needs to be updated SSPBUF is written with contents of SSPSR 3 1 8 9 ACK R/W = 0 1 3 4 5 Cleared in software 2 7 UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with low byte of address.
PIC16(L)F707 19.2.7 CLOCK STRETCHING 2 During any SCL low phase, any device on the I C bus may hold the SCL line low and delay, or pause, the transmission of data. This “stretching” of a transmission allows devices to slow down communication on the bus. The SCL line must be constantly sampled by the master to ensure that all devices on the bus have released SCL for more data. Stretching usually occurs after an ACK bit of a transmission, delaying the first bit of the next byte.
PIC16(L)F707 19.2.10 CLOCK SYNCHRONIZATION When the CKP bit is cleared, the SCL output is held low once it is sampled low. Therefore, the CKP bit will not stretch the SCL line until an external I2C master device has already asserted the SCL line low. The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have released SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (Figure 19-14). FIGURE 19-14: 19.2.
PIC16(L)F707 REGISTER 19-3: SSPCON: SYNCHRONOUS SERIAL PORT CONTROL REGISTER (I2C MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared
PIC16(L)F707 REGISTER 19-4: SSPSTAT: SYNCHRONOUS SERIAL PORT STATUS REGISTER (I2C MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: SPI Data Input Sample Phase bit 1 = Slew Rate Control (limiting) disabled. Operating in I2C Standard mode (100 kHz and 1 MHz).
PIC16(L)F707 REGISTER 19-5: SSPMSK: SSP MASK REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-1 MSK<7:1>: Mask bits 1 = The received address bit n is compared to SSPADD to detect I2C address match 0 = The received address bit n is not used to detect I2C address m
PIC16(L)F707 20.0 PROGRAM MEMORY READ The Flash program memory is readable during normal operation over the full VDD range of the device. To read data from Program Memory, five Special Function Registers (SFRs) are used: • • • • • PMCON1 PMDATL PMDATH PMADRL PMADRH The value written to the PMADRH:PMADRL register pair determines which program memory location is read. The read operation will be initiated by setting the RD bit of the PMCON1 register.
PIC16(L)F707 REGISTER 20-1: PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER U-1 U-0 U-0 U-0 U-0 U-0 U-0 R/S-0 — — — — — — — RD bit 7 bit 0 Legend: S = Setable bit, cleared in hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘1’ bit 6-1 Unimplemented: Read as ‘0’ bit 0 RD: Read Control bit 1 = Initiates a program memory read (The RD is cleared in har
PIC16(L)F707 REGISTER 20-4: PMADRH: PROGRAM MEMORY ADDRESS HIGH REGISTER U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — PMA12 PMA11 PMA10 PMA9 PMA8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 PMA<12:8>: Program Memory Read Address bits REGISTER 20-5: x = Bit is unknown PMADRL: PROGRAM MEMORY ADDRESS LOW REGISTER R/W-x R/W-x R/W-x
PIC16(L)F707 NOTES: DS41418B-page 184 2010-2011 Microchip Technology Inc.
PIC16(L)F707 21.0 POWER-DOWN MODE (SLEEP) 21.1 Wake-up from Sleep The Power-down mode is entered by executing a SLEEP instruction. The device can wake-up from Sleep through one of the following events: Upon entering Sleep mode, the following conditions exist: 1. 2. 3. 4. 5. 6. 1. WDT will be cleared but keeps running, if enabled. 2. PD bit of the STATUS register is cleared. 3. TO bit of the STATUS register is set. 4. CPU clock is disabled. 5.
PIC16(L)F707 21.1.1 WAKE-UP USING INTERRUPTS • If the interrupt occurs during or after the execution of a SLEEP instruction - SLEEP instruction will be completely executed - Device will immediately wake-up from Sleep - WDT and WDT prescaler will be cleared - TO bit of the STATUS register will be set - PD bit of the STATUS register will be cleared.
PIC16(L)F707 22.0 IN-CIRCUIT SERIAL PROGRAMMING™ (ICSP™) The device is placed into Program/Verify mode by holding the ICSPCLK and ICSPDAT pins low then raising the voltage on MCLR/VPP from 0v to VPP. In Program/Verify mode the program memory, user IDs and the Configuration Words are programmed through serial communications. The ICSPDAT pin is a bidirectional I/O used for transferring the serial data and the ISCPCLK pin is the clock input.
PIC16(L)F707 NOTES: DS41418B-page 188 2010-2011 Microchip Technology Inc.
PIC16(L)F707 23.0 INSTRUCTION SET SUMMARY The PIC16(L)F707 instruction set is highly orthogonal and is comprised of three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations Each PIC16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction.
PIC16(L)F707 TABLE 23-2: PIC16(L)F707 INSTRUCTION SET Mnemonic, Operands 14-Bit Opcode Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f – f, d f, d f, d f, d f, d f, d f, d f – f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move
PIC16(L)F707 23.2 Instruction Descriptions ADDLW Add literal and W Syntax: [ label ] ADDLW Operands: 0 k 255 Operation: (W) + k (W) Status Affected: C, DC, Z Description: The contents of the W register are added to the eight-bit literal ‘k’ and the result is placed in the W register. k BCF Bit Clear f Syntax: [ label ] BCF Operands: 0 f 127 0b7 Operation: 0 (f) Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared.
PIC16(L)F707 BTFSS Bit Test f, Skip if Set CLRWDT Clear Watchdog Timer Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRWDT Operands: 0 f 127 0b<7 Operands: None Operation: 00h WDT 0 WDT prescaler, 1 TO 1 PD Status Affected: TO, PD Description: CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set.
PIC16(L)F707 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f) - 1 (destination); skip if result = 0 Operation: (f) + 1 (destination), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in the W register.
PIC16(L)F707 MOVF Move f Syntax: [ label ] Operands: 0 f 127 d [0,1] MOVF f,d MOVWF Move W to f Syntax: [ label ] MOVWF Operands: 0 f 127 Operation: (W) (f) f Operation: (f) (dest) Status Affected: None Status Affected: Z Description: Description: The contents of register f is moved to a destination dependent upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself.
PIC16(L)F707 RETFIE Return from Interrupt RETLW Return with literal in W Syntax: [ label ] Syntax: [ label ] Operands: None Operands: 0 k 255 Operation: TOS PC, 1 GIE Operation: k (W); TOS PC Status Affected: None Status Affected: None Description: Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction.
PIC16(L)F707 RLF Rotate Left f through Carry SLEEP Enter Sleep mode Syntax: [ label ] Syntax: [ label ] SLEEP Operands: 0 f 127 d [0,1] Operands: None Operation: Operation: See description below Status Affected: C Description: The contents of register ‘f’ are rotated one bit to the left through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’.
PIC16(L)F707 SUBWF Subtract W from f XORLW Exclusive OR literal with W Syntax: [ label ] SUBWF f,d Syntax: [ label ] XORLW k Operands: 0 f 127 d [0,1] Operands: 0 k 255 (f) - (W) destination) Operation: (W) .XOR. k W) Operation: Status Affected: C, DC, Z Description: SWAPF Status Affected: Z Description: The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register.
PIC16(L)F707 NOTES: DS41418B-page 198 2010-2011 Microchip Technology Inc.
PIC16(L)F707 24.
PIC16(L)F707 24.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 24.
PIC16(L)F707 24.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC16(L)F707 24.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 24.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
PIC16(L)F707 25.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings(†) Ambient temperature under bias....................................................................................................... -40°C to +125°C Storage temperature ........................................................................................................................ -65°C to +150°C Voltage on VDD with respect to VSS, PIC16F707 ............................................................................... -0.
PIC16(L)F707 25.1 DC Characteristics: PIC16(L)F707-I/E (Industrial, Extended) PIC16LF707 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F707 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param. No. D001 Sym. VDD Characteristic VDR Units PIC16LF707 1.8 1.8 2.3 2.5 — — — — 3.6 3.6 3.6 3.
PIC16(L)F707 FIGURE 25-1: POR AND POR REARM WITH SLOW RISING VDD VDD VPOR VPORR VSS NPOR POR REARM VSS TVLOW(2) Note 1: 2: 3: TPOR(3) When NPOR is low, the device is held in Reset. TPOR 1 s typical. TVLOW 2.7 s typical. 2010-2011 Microchip Technology Inc.
PIC16(L)F707 25.2 DC Characteristics: PIC16(L)F707-I/E (Industrial, Extended) PIC16LF707 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F707 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Conditions Min. Typ† Max.
PIC16(L)F707 25.2 DC Characteristics: PIC16(L)F707-I/E (Industrial, Extended) (Continued) PIC16LF707 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F707 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Conditions Min. Typ† Max.
PIC16(L)F707 25.3 DC Characteristics: PIC16(L)F707-I/E (Power-Down) PIC16LF707 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F707 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Power-down Base Current Min. Typ† Conditions Max. +85°C Max. +125°C Units 0.7 3.
PIC16(L)F707 25.3 DC Characteristics: PIC16(L)F707-I/E (Power-Down) (Continued) PIC16LF707 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F707 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics Min. Power-down Base Current (IPD) D027 D027 Typ† Max.
PIC16(L)F707 25.3 DC Characteristics: PIC16(L)F707-I/E (Power-Down) (Continued) PIC16LF707 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16F707 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Device Characteristics D028D D028D D028E D028E † Note 1: 2: 3: 4: 5: 6: Min.
PIC16(L)F707 25.4 DC Characteristics: PIC16(L)F707-I/E DC CHARACTERISTICS Param No. Sym. VIL Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Min. Typ† Max. Units — — with Schmitt Trigger buffer with I2C™ levels Conditions — 0.8 V 4.5V VDD 5.5V — 0.15 VDD V 1.8V VDD 4.5V — — 0.2 VDD V 2.0V VDD 5.5V — — 0.
PIC16(L)F707 25.4 DC Characteristics: PIC16(L)F707-I/E (Continued) DC CHARACTERISTICS Param No. D130 Sym. EP Min. Typ† Max. Units Conditions Cell Endurance 100 1k — E/W Temperature during programming: 10°C TA 40°C VDD for Read VMIN — — V Voltage on MCLR/VPP during Erase/Program 8.0 — 9.0 V Temperature during programming: 10°C TA 40°C VDD for Bulk Erase 2.7 3 — V Temperature during programming: 10°C TA 40°C VPEW VDD for Write or Row Erase 2.
PIC16(L)F707 25.5 Thermal Considerations Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. TH01 TH02 Sym Characteristic Typ Units JA Thermal Resistance Junction to Ambient 47.2 C/W 40-pin PDIP package 46 C/W 44-pin TQFP package JC TH03 TJMAX TH04 PD TH05 Thermal Resistance Junction to Case Maximum Junction Temperature Power Dissipation PINTERNAL Internal Power Dissipation Conditions 24.
PIC16(L)F707 25.6 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2.
PIC16(L)F707 25.7 AC Characteristics: PIC16F707-I/E FIGURE 25-3: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1/CLKIN OS02 OS04 OS04 OS03 OSC2/CLKOUT (LP,XT,HS Modes) OSC2/CLKOUT (CLKOUT Mode) PIC16F707 VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C FIGURE 25-4: VDD (V) 5.5 3.6 2.5 2.3 2.0 1.8 0 4 10 16 20 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 25-1 for each Oscillator mode’s supported frequencies.
PIC16(L)F707 PIC16LF707 VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C VDD (V) FIGURE 25-5: 3.6 2.5 2.3 2.0 1.8 0 4 16 10 20 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 25-1 for each Oscillator mode’s supported frequencies. HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE FIGURE 25-6: 125 + 5% 85 Temperature (°C) ± 3% 60 ± 2% 25 0 -20 + 5% -40 1.8 2.0 2.5 3.0 3.3(2) 3.5 4.0 4.5 5.0 5.
PIC16(L)F707 TABLE 25-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. OS01 Sym. FOSC Characteristic External CLKIN Frequency(1) Oscillator Frequency OS02 TOSC (1) External CLKIN Period(1) Oscillator Period(1) OS03 TCY Instruction Cycle Time(1) OS04* TosH, TosL External CLKIN High, External CLKIN Low OS05* TosR, TosF External CLKIN Rise, External CLKIN Fall Min. Typ† Max.
PIC16(L)F707 TABLE 25-2: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. OS08 Sym. Characteristic HFOSC Internal Calibrated HFINTOSC Frequency(2) OS08A MFOSC Internal Calibrated MFINTOSC Frequency(2) OS10* Freq. Tolerance Min. Typ† Max. Units 2% — 16.0 — MHz 0°C TA +85°C, VDD V 5% — 16.
PIC16(L)F707 TABLE 25-3: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. OS11 Sym. TosH2ckL Characteristic Min. Typ† Max. Units Conditions Fosc to CLKOUT (1) — — 70 ns VDD = 3.3-5.0V (1) — — 72 ns VDD = 3.3-5.
PIC16(L)F707 FIGURE 25-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Start-Up Time Internal Reset(1) Watchdog Timer Reset(1) 31 34 34 I/O pins Note 1: Asserted low.
PIC16(L)F707 TABLE 25-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. Sym. Characteristic Min. Typ† Max. Units Conditions 30 TMCL MCLR Pulse Width (low) 2 5 — — — — s s VDD = 3.3-5V, -40°C to +85°C VDD = 3.3-5V 31 TWDTLP Low Power Watchdog Timer Timeout Period (No Prescaler) 10 18 27 ms VDD = 3.
PIC16(L)F707 FIGURE 25-10: TIMER0/A/B AND TIMER1/3 EXTERNAL CLOCK TIMINGS T0CKI/TACKI/TBCKI 40 41 42 T1CKI/T3CKI 45 46 49 47 TMRx TABLE 25-5: TIMER0/A/B AND TIMER1/3 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. 40* Sym. TT0H 41* TT0L Characteristic T0CKI/TACKI/TBCKI High Pulse Width T0CKI/TACKI/TBCKI Low Pulse Width No Prescaler With Prescaler No Prescaler With Prescaler Min. Typ† Max. Units 0.
PIC16(L)F707 FIGURE 25-11: CAPTURE/COMPARE/PWM TIMINGS (CCP) CCPx (Capture mode) CC01 CC02 CC03 Note: Refer to Figure 25-2 for load conditions. TABLE 25-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP) Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param Sym. No. CC01* TccL CC02* TccH CC03* TccP * † Characteristic CCPx Input Low Time CCPx Input High Time Min. Typ† Max. Units No Prescaler 0.
PIC16(L)F707 TABLE 25-8: PIC16F707 A/D CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. Sym. Characteristic AD130* TAD AD131 TCNV AD132* TACQ Min. Typ† Max. Units Conditions A/D Clock Period 1.0 — 9.0 s TOSC-based A/D Internal RC Oscillator Period 1.0 2.0 6.0 s ADCS<1:0> = 11 (ADRC mode) Conversion Time (not including Acquisition Time)(1) — 10.
PIC16(L)F707 FIGURE 25-13: PIC16F707 A/D CONVERSION TIMING (SLEEP MODE) BSF ADCON0, GO (TOSC/2 + TCY(1)) AD134 1 TCY AD131 Q4 AD130 A/D CLK 7 A/D Data 6 5 4 3 2 1 0 NEW_DATA OLD_DATA ADRES ADIF 1 TCY GO DONE Sampling Stopped AD132 Sample Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
PIC16(L)F707 FIGURE 25-15: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING CK US125 DT US126 Note: Refer to Figure 25-2 for load conditions. TABLE 25-10: USART SYNCHRONOUS RECEIVE REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param. No. Symbol Characteristic Min. US125 TDTV2CKL SYNC RCV (Master and Slave) Data-hold before CK (DT hold time) US126 TCKL2DTL FIGURE 25-16: Data-hold after CK (DT hold time) Max.
PIC16(L)F707 FIGURE 25-17: SPI MASTER MODE TIMING (CKE = 1, SMP = 1) SS SP81 SCK (CKP = 0) SP71 SP72 SP79 SP73 SCK (CKP = 1) SP80 SP78 LSb bit 6 - - - - - -1 MSb SDO SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 Note: Refer to Figure 25-2 for load conditions.
PIC16(L)F707 FIGURE 25-19: SS SPI SLAVE MODE TIMING (CKE = 1) SP82 SP70 SP83 SCK (CKP = 0) SP71 SP72 SCK (CKP = 1) SP80 SDO MSb bit 6 - - - - - -1 LSb SP77 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 Note: Refer to Figure 25-2 for load conditions. DS41418B-page 228 2010-2011 Microchip Technology Inc.
PIC16(L)F707 TABLE 25-11: SPI MODE REQUIREMENTS Param No. Symbol Characteristic SP70* TSSL2SCH, SS to SCK or SCK input TSSL2SCL Min. Typ† Max.
PIC16(L)F707 TABLE 25-12: I2C™ BUS START/STOP BITS REQUIREMENTS Param No. Symbol SP90* TSU:STA SP91* THD:STA SP92* TSU:STO SP93 THD:STO Stop condition Characteristic Start condition Typ 4700 — Max. Units — Setup time 400 kHz mode 600 — — Start condition 100 kHz mode 4000 — — Hold time 400 kHz mode 600 — — Stop condition 100 kHz mode 4700 — — Setup time Hold time * 100 kHz mode Min.
PIC16(L)F707 TABLE 25-13: I2C™ BUS DATA REQUIREMENTS Param. No. Symbol SP100* THIGH Characteristic Clock high time Min. Max. Units Conditions 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz 1.5TCY — 100 kHz mode 4.7 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.
PIC16(L)F707 TABLE 25-14: CAP SENSE OSCILLATOR SPECIFICATIONS Param. No. CS01 CS02 CS03 Symbol Characteristic Current Source ISRC Current Sink ISNK VCHYST Cap Hysteresis Min. Typ† Max. Units High — -5.8 -6 A Medium — -1.1 -3.2 A Low — -0.2 -0.9 A High — 6.6 6 A Medium — 1.3 3.2 A Low — 0.24 0.9 A High — 525 — mV Medium — 375 — mV Low — 280 — mV Conditions -40, -85°C -40, -85°C VCTH-VCTL * These parameters are characterized but not tested.
PIC16(L)F707 26.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
PIC16(L)F707 FIGURE 26-2: PIC16LF707 MAXIMUM IDD vs. FOSC OVER VDD, EC MODE 2,400 2,200 2,000 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 3.6V 3.3V 1,800 3V IDD (µA) 1,600 2.5V 1,400 1,200 2V 1,000 1.8V 800 600 400 200 0 1 MHz 4 MHz 8 MHz 12 MHz 16 MHz 20 MHz FOSC FIGURE 26-3: PIC16F707 TYPICAL IDD vs. FOSC OVER VDD, EC MODE, VCAP = 0.1µF 2,000 1,800 5V Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 3.
PIC16(L)F707 FIGURE 26-4: PIC16LF707 TYPICAL IDD vs. FOSC OVER VDD, EC MODE 2,200 2,000 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 3.6V 1,800 3.3V 3V 1,600 IDD (µA) 1,400 2.5V 1,200 2V 1,000 1.8V 800 600 400 200 0 1 MHz 4 MHz 8 MHz 12 MHz 16 MHz 20 MHz FOSC PIC16F707 MAXIMUM IDD vs. VDD OVER FOSC, EXTRC MODE, VCAP = 0.
PIC16(L)F707 FIGURE 26-6: PIC16LF707 MAXIMUM IDD vs. VDD OVER FOSC, EXTRC MODE 500 450 4 MHz Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 400 350 IDD (µA) 300 250 200 150 1 MHz 100 50 0 1.8 2 2.5 3 3.3 3.6 VDD (V) FIGURE 26-7: PIC16F707 TYPICAL IDD vs. VDD OVER FOSC, EXTRC MODE, VCAP = 0.1µF 450 400 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 4 MHz 350 IDD (µA) 300 250 200 150 1 MHz 100 50 0 1.
PIC16(L)F707 FIGURE 26-8: PIC16LF707 TYPICAL IDD vs. VDD OVER FOSC, EXTRC MODE 450 400 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 4 MHz 350 IDD (µA) 300 250 200 150 1 MHz 100 50 0 1.8 2 2.5 3 3.3 3.6 VDD (V) FIGURE 26-9: PIC16F707 MAXIMUM IDD vs. FOSC OVER VDD, HS MODE, VCAP = 0.1µF 2.4 2.2 2 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 5V 4.5V 3.6V 1.8 3V 1.6 IDD (mA) 1.4 1.2 1 0.8 0.6 0.4 0.
PIC16(L)F707 FIGURE 26-10: PIC16LF707 MAXIMUM IDD vs. FOSC OVER VDD, HS MODE 2.50 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 3.6V 2.00 3.3V 3V 1.50 IDD (mA) 2.5V 1.00 0.50 0.00 4 MHz 6 MHz 8 MHz 10 MHz 13 MHz 16 MHz 20 MHz Fosc FIGURE 26-11: 2.00 PIC16F707 TYPICAL IDD vs. FOSC OVER VDD, HS MODE, VCAP = 0.1µF Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 5V 4.5V 3.6V 3V IDD (mA) 1.50 1.00 0.50 0.
PIC16(L)F707 FIGURE 26-12: PIC16LF707 TYPICAL IDD vs. FOSC OVER VDD, HS MODE 2.50 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 2.00 3.6V 3.3V 3V IDD (mA) 1.50 2.5V 1.00 0.50 0.00 4 MHz 6 MHz 8 MHz 10 MHz 13 MHz 16 MHz 20 MHz Fosc FIGURE 26-13: PIC16F707 MAXIMUM IDD vs. VDD OVER FOSC, XT MODE, VCAP = 0.1µF 600 500 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 4 MHz IDD (µA) 400 300 1 MHz 200 100 0 1.
PIC16(L)F707 FIGURE 26-14: PIC16LF707 MAXIMUM IDD vs. VDD OVER FOSC, XT MODE 600 500 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 4 MHz IDD (µA) 400 300 1 MHz 200 100 0 1.8 2 2.5 3 3.3 3.6 VDD (V) FIGURE 26-15: PIC16F707 TYPICAL IDD vs. VDD OVER FOSC, XT MODE, VCAP = 0.1µF 600 500 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 4 MHz IDD (µA) 400 300 1 MHz 200 100 0 1.8 2 2.5 3 3.3 3.6 4.2 4.
PIC16(L)F707 FIGURE 26-16: PIC16LF707 TYPICAL IDD vs. VDD OVER FOSC, XT MODE 600 500 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 4 MHz IDD (µA) 400 300 1 MHz 200 100 0 1.8 2 2.5 3 3.3 3.6 VDD (V) FIGURE 26-17: PIC16F707 IDD vs. VDD, LP MODE, VCAP = 0.1µF 20.0 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 17.5 IDD (µA) 32 kHz Maximum 15.0 VDD (V) 32 kHz Typical 12.5 10.0 1.
PIC16(L)F707 FIGURE 26-18: PIC16LF707 IDD vs. VDD, LP MODE 30 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 25 32 kHz Maximum IDD (µA) 20 15 32 kHz Typical 10 5 1.8 3 3.3 3.6 VDD (V) FIGURE 26-19: PIC16F707 MAXIMUM IDD vs. FOSC OVER VDD, INTOSC MODE, VCAP = 0.1µF 210 200 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 5V 190 180 3.6V IDD (µA) 170 2.5V 160 150 1.8V 140 130 120 110 62.
PIC16(L)F707 FIGURE 26-20: PIC16LF707 MAXIMUM IDD vs. FOSC OVER VDD, INTOSC MODE 170 160 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 3.6V IDD (µA) 150 3V 2.5V 140 130 1.8V 120 110 100 62.5 kHz 125 kHz 250 kHz 500 kHz FOSC FIGURE 26-21: PIC16F707 MAXIMUM IDD vs. FOSC OVER VDD, INTOSC MODE, VCAP = 0.1µF 2,000 1,800 5V Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 3.6V 1,600 2.5V 1,400 IDD (µA) 1,200 1.
PIC16(L)F707 FIGURE 26-22: PIC16LF707 MAXIMUM IDD vs. FOSC OVER VDD, INTOSC MODE 2,250 2,000 s Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 3.6V 1,750 3V 1,500 IDD (µA) 2.5V 1,250 1.8V 1,000 750 500 250 0 2 MHz 4 MHz 8 MHz 16 MHz FOSC FIGURE 26-23: PIC16F707 TYPICAL IDD vs. FOSC OVER VDD, INTOSC MODE, VCAP = 0.1µF 160 150 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 5V IDD (µA) 140 3.6V 130 2.
PIC16(L)F707 FIGURE 26-24: PIC16LF707 TYPICAL IDD vs. FOSC OVER VDD, INTOSC MODE 140 130 3.6V Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 3V 120 2.5V IDD (µA) 110 100 1.8V 90 80 70 62.5 kHz 125 kHz 250 kHz 500 kHz FOSC FIGURE 26-25: PIC16F707 TYPICAL IDD vs. FOSC OVER VDD, INTOSC MODE, VCAP = 0.1µF 2,000 1,800 1,600 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 5V 3.6V 1,400 2.5V IDD (µA) 1,200 1,000 1.
PIC16(L)F707 FIGURE 26-26: PIC16LF707 TYPICAL IDD vs. FOSC OVER VDD, INTOSC MODE 2,000 3.6V Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 1,800 1,600 3V 1,400 2.5V IDD (µA) 1,200 1,000 1.8V 800 600 400 200 0 2 MHz 4 MHz 8 MHz 16 MHz VDD (V) FIGURE 26-27: PIC16F707 MAXIMUM BASE IPD vs. VDD, VCAP = 0.1µF 25 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 20 125°C IPD (µA) 15 85°C 10 5 0 1.8V 2V 3V 3.
PIC16(L)F707 FIGURE 26-28: PIC16LF707 MAXIMUM BASE IPD vs. VDD 7 6 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 125°C IPD (µA) 5 4 3 2 85°C 1 0 1.8V 2V 2.5V 3V 3.6V VDD (V) FIGURE 26-29: PIC16F707 TYPICAL BASE IPD vs. VDD, VCAP = 0.1µF 8 7 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 6 IPD (µA) 25°C 5 4 3 2 1.8V 2V 3V 3.6V 4V 5V 5.5V VDD (V) 2010-2011 Microchip Technology Inc.
PIC16(L)F707 FIGURE 26-30: PIC16LF707 TYPICAL BASE IPD vs. VDD 250 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 200 25°C IPD (nA) 150 100 50 0 1.8V 2V 2.5V 3V 3.6V VDD (V) FIGURE 26-31: PIC16F707 FIXED VOLTAGE REFERENCE IPD vs. VDD, VCAP = 0.1µF 70 60 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Max. 125°C 50 Max. 85°C IPD (µA) 40 30 Typ. 25°C 20 10 0 1.8V 2V 3V 3.6V 5V 5.
PIC16(L)F707 FIGURE 26-32: PIC16LF707 FIXED VOLTAGE REFERENCE IPD vs. VDD 25 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Max. 125°C 20 15 IPD (µA) Max. 85°C 10 Typ. 25°C 5 0 1.8V 2V 2.5V 3V 3.6V VDD (V) FIGURE 26-33: PIC16F707 BOR IPD vs. VDD, VCAP = 0.1µF 70 60 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Max. 125°C 50 IPD (µA) 40 Max. 85°C 30 Typ. 25°C 20 10 0 2V 3V 3.6V 5V 5.
PIC16(L)F707 FIGURE 26-34: PIC16LF707 BOR IPD vs. VDD 30 25 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Max. 125°C IPD (µA) 20 15 Max. 85°C 10 Typ. 25°C 5 0 2V 2.5V 3V 3.6V VDD (V) FIGURE 26-35: PIC16F707 CAP SENSE HIGH POWER IPD vs. VDD, VCAP = 0.1µF 70 60 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Max. 125°C Max. 85°C 50 Typ. 25°C IPD (µA) 40 30 20 10 0 1.8V 2V 3V 3.6V 5V 5.
PIC16(L)F707 FIGURE 26-36: PIC16LF707 CAP SENSE HIGH POWER IPD vs. VDD 60 50 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Max. 125°C Max. 85°C 40 IPD (µA) Typ. 25°C 30 20 10 0 1.8V 2V 2.5V 3V 3.6V VDD (V) FIGURE 26-37: PIC16F707 CAP SENSE MEDIUM POWER IPD vs. VDD, VCAP = 0.1µF 30 25 Max. 125°C Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 20 IPD (µA) Max. 85°C 15 Typ. 25°C 10 5 0 1.8V 2V 3V 3.
PIC16(L)F707 FIGURE 26-38: PIC16LF707 CAP SENSE MEDIUM POWER IPD vs. VDD 20 18 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Max. 125°C 16 14 IPD (µA) 12 10 8 Max. 85°C 6 Typ. 25°C 4 2 0 1.8V 2V 2.5V 3V 3.6V VDD (V) FIGURE 26-39: PIC16F707 CAP SENSE LOW POWER IPD vs. VDD, VCAP = 0.1µF 30 25 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Max. 125°C IPD (µA) 20 Max. 85°C 15 10 Typ. 25°C 5 0 1.
PIC16(L)F707 FIGURE 26-40: PIC16LF707 CAP SENSE LOW POWER IPD vs. VDD 18 16 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Max. 125°C 14 12 IPD (µA) 10 8 6 Max. 85°C 4 Typ. 25°C 2 0 1.8V 2V 2.5V 3V 3.6V VDD (V) FIGURE 26-41: PIC16F707 T1OSC 32 kHz IPD vs. VDD, VCAP = 0.1µF 16 14 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Max. 85°C 12 IPD (µA) 10 Typ. 25° C 8 6 4 2 0 1.8V 2V 3V 3.6V 5V 5.
PIC16(L)F707 FIGURE 26-42: PIC16LF707 T1OSC 32 kHz IPD vs. VDD 4.0 3.5 Max. 85°C Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 3.0 2.5 IPD (µA) Typ. 2.0 1.5 1.0 0.5 0.0 1.8V 2V 2.5V 3V 3.6V VDD (V) FIGURE 26-43: PIC16F707 TYPICAL ADC IPD vs. VDD, VCAP = 0.1µF 7.5 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Typ. 25°C 7.0 IPD (µA) 6.5 6.0 5.5 5.0 1.8V 2V 3V 3.6V 5V 5.
PIC16(L)F707 FIGURE 26-44: PIC16LF707 TYPICAL ADC IPD vs. VDD 250 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Typ. 25°C 200 IPD (nA) 150 100 50 0 1.8V 2V 2.5V 3V 3.6V VDD (V) FIGURE 26-45: PIC16F707 ADC IPD vs. VDD, VCAP = 0.1µF 25 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Max. 125°C IPD (µA) 20 15 Max. 85°C 10 5 1.8V 2V 3V 3.6V 5V 5.5V VDD (V) 2010-2011 Microchip Technology Inc.
PIC16(L)F707 FIGURE 26-46: PIC16LF707 ADC IPD vs. VDD 8 7 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Max. 125°C 6 IPD (µA) 5 4 3 2 Max. 85°C 1 0 1.8V 2V 2.5V 3V 3.6V VDD (V) FIGURE 26-47: PIC16F707 WDT IPD vs. VDD, VCAP = 0.1µF 18 16 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Max. 85°C 14 12 IPD (µA) 10 Typ. 25°C 8 6 4 2 0 1.8V 2V 3V 3.6V 5V 5.
PIC16(L)F707 FIGURE 26-48: PIC16LF707 WDT IPD vs. VDD 3.5 3.0 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Max. 85°C 2.5 IPD (µA) 2.0 1.5 Typ. 25°C 1.0 0.5 0.0 1.8V 2V 2.5V 3V 3.6V VDD (V) FIGURE 26-49: TTL INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE 1.8 1.6 Maximum: Mean + 3 (-40°C to 125°C) Typical: Mean @25°C Minimum: Mean - 3 (-40°C to 125°C) 1.4 Max. -40° VIN (V) 1.2 Typ. 25° 1 Min. 125° 0.8 0.6 0.4 1.8 3.6 5.
PIC16(L)F707 FIGURE 26-50: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE 3.5 3.0 Maximum: Mean + 3 (-40°C to 125°C) Typical: Mean @25°C Minimum: Mean - 3 (-40°C to 125°C) VIHMax. -40°C 2.5 VIN (V) 2.0 1.5 VIHMin. 125°C 1.0 0.5 0.0 1.8 3.6 5.5 VDD (V) FIGURE 26-51: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE 3.0 2.5 Maximum: Mean + 3 (-40°C to 125°C) Typical: Mean @25°C Minimum: Mean - 3 (-40°C to 125°C) VIL Max. -40°C VIN (V) 2.0 1.5 1.0 VIL Min.
PIC16(L)F707 FIGURE 26-52: VOH vs. IOH OVER TEMPERATURE, VDD = 5.5V 5.6 Maximum: Mean + 3 (-40°C to 125°C) Typical: Mean @25°C Minimum: Mean - 3 (-40°C to 125°C) 5.5 VOH (V) 5.4 5.3 Max. -40° Typ. 25° 5.2 Min. 125° 5.1 5 -0.2 -1.0 -1.8 -2.6 -3.4 -4.2 -5.0 IOH (mA) FIGURE 26-53: VOH vs. IOH OVER TEMPERATURE, VDD = 3.6V 3.8 Maximum: Mean + 3 (-40°C to 125°C) Typical: Mean @25°C Minimum: Mean - 3 (-40°C to 125°C) 3.6 3.4 VOH (V) Max. -40° 3.2 Typ. 25° 3 Min. 125° 2.8 2.6 -0.
PIC16(L)F707 FIGURE 26-54: VOH vs. IOH OVER TEMPERATURE, VDD = 1.8V 2 Maximum: Mean + 3 (-40°C to 125°C) Typical: Mean @25°C Minimum: Mean - 3 (-40°C to 125°C) 1.8 1.6 Max. -40° 1.4 VOH (V) 1.2 Typ. 25° 1 0.8 0.6 Min. 125° 0.4 0.2 0 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 -2.0 IOH (mA) FIGURE 26-55: VOL vs. IOL OVER TEMPERATURE, VDD = 5.5V 0.5 Maximum: Mean + 3 (-40°C to 125°C) Typical: Mean @25°C Minimum: Mean - 3 (-40°C to 125°C) 0.45 0.4 0.35 Max. 125° VOL (V) 0.3 0.
PIC16(L)F707 FIGURE 26-56: VOL vs. IOL OVER TEMPERATURE, VDD = 3.6 0.9 Maximum: Mean + 3 (-40°C to 125°C) Typical: Mean @25°C Minimum: Mean - 3 (-40°C to 125°C) 0.8 0.7 0.6 Max. 125° VOL (V) 0.5 0.4 Typ. 25° 0.3 0.2 Min. -40° 0.1 0 4.0 5.0 FIGURE 26-57: 6.0 7.0 IOL (mA) 8.0 9.0 10.0 VOL vs. IOL OVER TEMPERATURE, VDD = 1.8V 1.2 1 Maximum: Mean + 3 (-40°C to 125°C) Typical: Mean @25°C Minimum: Mean - 3 (-40°C to 125°C) 0.8 VOL (V) Max. 125° 0.6 0.4 0.2 Min. -40° 0 0.0 0.4 0.
PIC16(L)F707 FIGURE 26-58: PIC16F707 PWRT PERIOD 105 95 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Max. -40°C TIME (ms) 85 75 Typ. 25°C 65 Min. 125°C 55 45 1.8V 2V 2.2V 2.4V 3V 3.6V 4V 4.5V 5V 5.5V VDD FIGURE 26-59: PIC16F707 WDT TIME-OUT PERIOD 24.00 22.00 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Max. -40°C 20.00 TIME (ms) 18.00 Typ. 25°C 16.00 14.00 Min. 125°C 12.00 10.00 1.8V 2V 2.2V 2.
PIC16(L)F707 FIGURE 26-60: PIC16F707 HFINTOSC WAKE-UP FROM SLEEP START-UP TIME 6.0 5.5 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) 5.0 4.5 Max. TIME (us) 4.0 3.5 3.0 Typ. 2.5 2.0 1.5 1.0 1.8V 2V 3V 3.6V 4V 4.5V 5V 5.5V VDD FIGURE 26-61: PIC16F707 A/D INTERNAL RC OSCILLATOR PERIOD 6.0 5.0 Typical: Statistical Mean @25°C Maximum: Mean (Worst-Case Temp) + 3 (-40°C to 125°C) Period (µs) 4.0 3.0 Max. Min. 2.0 1.0 0.0 1.8V 3.6V 5.
PIC16(L)F707 FIGURE 26-62: PIC16F707 CAP SENSE OUTPUT CURRENT, POWER MODE = HIGH 20000 Min. Sink -40°C 15000 Typ. Sink 25°C Current (nA) 10000 Max. Sink 85°C 5000 0 Min. Source 85°C -5000 Typ. Source 25°C -10000 Max. Source -40°C -15000 1.8 2 2.5 3 3.2 3.6 4 4.5 5 5.5 VDD(V) FIGURE 26-63: PIC16F707 CAP SENSE OUTPUT CURRENT, POWER MODE = MEDIUM 3000 Max. Sink -40°C 2000 Typ. Sink 25°C 1000 Current (nA) Min. Sink 85°C 0 Min. Source 85°C -1000 Typ. Source 25°C -2000 Max.
PIC16(L)F707 FIGURE 26-64: PIC16F707 CAP SENSE OUTPUT CURRENT, POWER MODE = LOW 600 Max. Sink 85°C 400 Typ. Sink 25°C 200 Min. Sink -40°C Current (nA) 0 Min. Source 85°C -200 Typ. Source 25°C -400 -600 Max. Source -40°C -800 1.8 2 2.5 3 3.2 3.6 4 4.5 5 5.5 VDD(V) FIGURE 26-65: PIC16F707 CAP SENSOR HYSTERESIS, POWER MODE = HIGH 700 Max. 125°C Max. 85°C 600 mV Typ. 25°C 500 Min. 0°C Min. -40°C 400 300 1.8 2.0 2.5 3.0 3.2 3.6 4.0 4.5 5.0 5.
PIC16(L)F707 FIGURE 26-66: PIC16F707 CAP SENSOR HYSTERESIS, POWER MODE = MEDIUM 550 500 Max. 125°C mV 450 Max. 85°C 400 Typ. 25°C 350 Min. 0°C 300 Min. -40°C 250 1.8 2.0 2.5 3.0 3.2 3.6 4.0 4.5 5.0 5.5 VDD(V) FIGURE 26-67: PIC16F707 CAP SENSOR HYSTERESIS, POWER MODE = LOW 450 Max. 125°C 400 Max. 85°C mV 350 300 Typ. 25°C 250 Min. 0°C 200 Min -40°C 150 1.8 2.0 2.5 3.0 3.2 3.6 4.0 4.5 5.0 5.5 VDD(V) DS41418B-page 266 2010-2011 Microchip Technology Inc.
PIC16(L)F707 FIGURE 26-68: TYPICAL FVR (X1 AND X2) VS. SUPPLY VOLTAGE (V) NORMALIZED AT 3.0V 1.5 Percent Change (%) 1 0.5 0 -0.5 -1 -1.5 1.8 2.5 3 3.6 4.2 5.5 Voltage FIGURE 26-69: TYPICAL FVR CHANGE VS. TEMPERATURE NORMALIZED AT 25°C 1.5 1 Percent Change (%) 0.5 0 -0.5 -1 -1.5 -2 -2.5 -3 -40 0 45 85 125 Temperature (°C) 2010-2011 Microchip Technology Inc.
PIC16(L)F707 NOTES: DS41418B-page 268 2010-2011 Microchip Technology Inc.
PIC16(L)F707 27.0 PACKAGING INFORMATION 27.1 Package Marking Information 40-Lead PDIP (600 mil) XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN Example PIC16F707 -I/P e3 10033K1 44-Lead QFN (8x8x0.9 mm) PIN 1 Example PIN 1 XXXXXXXXXXX XXXXXXXXXXX XXXXXXXXXXX YYWWNNN 44-Lead TQFP (10x10x1 mm) XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN Legend: XX...
PIC16(L)F707 40-Lead UQFN (5x5x0.5 mm) PIN 1 Example PIN 1 PIC16F707 -I/MV e3 10033K1 Legend: XX...X Y YY WW NNN e3 * Note: * Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
PIC16(L)F707 27.2 Package Details The following sections give the technical details of the packages. 4 & ' !& " & 5 # * !( ! ! & 5 % & & # & && 366*** ' '6 5 N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB 7 &! ' ! : ' &! 8"') % ! 8,9.
PIC16(L)F707 ! " # $ % &'& ! 4 & ' !& " & 5 # * !( ! ! & 5 % & & # & && 366*** ' '6 5 D D2 EXPOSED PAD e E E2 b 2 2 1 N 1 N NOTE 1 TOP VIEW K L BOTTOM VIEW A A3 A1 7 &! ' ! : ' &! 8"') % ! :: . . 8 8 8; < & ; 9 & ? & # %% 1 , & & 5 !! - ; > #& . .$ .
PIC16(L)F707 ! " # $ % &'& ! 4 & ' !& " & 5 # * !( ! ! & 5 % & & # & && 366*** ' '6 5 2010-2011 Microchip Technology Inc.
PIC16(L)F707 () ! * # ( + '+ '+ " ,- ( ! 4 & ' !& " & 5 # * !( ! ! & 5 % & & # & && 366*** ' '6 5 D D1 E e E1 N b NOTE 1 1 2 3 NOTE 2 α A c φ β L A1 7 &! ' ! : ' &! 8"') % : #! A2 L1 :: . .
PIC16(L)F707 () ! * # ( + '+ '+ " ,- ( ! 4 & ' !& " & 5 # * !( ! ! & 5 % & & # & && 366*** ' '6 5 2010-2011 Microchip Technology Inc.
PIC16(L)F707 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41418B-page 276 2010-2011 Microchip Technology Inc.
PIC16(L)F707 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2010-2011 Microchip Technology Inc.
PIC16(L)F707 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41418B-page 278 2010-2011 Microchip Technology Inc.
PIC16(L)F707 APPENDIX A: DATA SHEET REVISION HISTORY Revision A (4/2010) Original release of this data sheet. Revision B (4/2011) APPENDIX B: This discusses some of the issues in migrating from other PIC® devices to the PIC16F707 family of devices. Note: This device has been designed to perform to the parameters of its data sheet. It has been tested to an electrical specification designed to determine its conformance with these parameters.
PIC16(L)F707 NOTES: DS41418B-page 280 2010-2011 Microchip Technology Inc.
PIC16(L)F707 INDEX A Receive .................................................... 157 Transmit ................................................... 156 Reception ......................................................... 157 Transmission .................................................... 156 A/D Specifications.................................................... 223, 224 Absolute Maximum Ratings .............................................. 203 AC Characteristics Industrial and Extended ..................
PIC16(L)F707 Setup for PWM Operation ......................................... 137 Timer Resources....................................................... 129 CCP. See Capture/Compare/PWM (CCP) CCP1CON Register ............................................................ 21 CCP2CON Register ............................................................ 21 CCPR1H Register ............................................................... 21 CCPR1L Register...........................................................
PIC16(L)F707 Associated registers w/ Interrupts............................... 49 Configuration Word w/ LDO ........................................ 51 Interrupt-on-Change.................................................... 57 Synchronous Serial Port Interrupt............................... 48 INTOSC Specifications ..................................................... 218 IOCB Register ..................................................................... 59 L Load Conditions ...............................
PIC16(L)F707 RE3 ............................................................................. 69 PORTE Register ................................................................. 67 Power-Down Mode (Sleep) ............................................... 185 Associated Registers ................................................ 186 Power-on Reset .................................................................. 33 Power-up Timer (PWRT)..................................................... 33 Specifications ..
PIC16(L)F707 Specifications............................................................ 222 Timer1 ............................................................................... 101 Asynchronous Counter Mode ................................... 104 Reading and Writing ......................................... 104 Modes of Operation .................................................. 103 Oscillator ................................................................... 104 Prescaler...............................
PIC16(L)F707 NOTES: DS41418B-page 286 2010-2011 Microchip Technology Inc.
PIC16(L)F707 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
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PIC16(L)F707 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO.
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