Datasheet

PIC16F631/677/685/687/689/690
DS41262E-page 200 © 2008 Microchip Technology Inc.
14.2 Reset
The PIC16F631/677/685/687/689/690 differentiates
between various kinds of Reset:
a) Power-on Reset (POR)
b) WDT Reset during normal operation
c) WDT Reset during Sleep
d) MCLR
Reset during normal operation
e) MCLR Reset during Sleep
f) Brown-out Reset (BOR)
Some registers are not affected in any Reset condition;
their status is unknown on POR and unchanged in any
other Reset. Most other registers are reset to a “Reset
state” on:
• Power-on Reset
•MCLR
Reset
•MCLR Reset during Sleep
•WDT Reset
• Brown-out Reset (BOR)
They are not affected by a WDT Wake-up since this is
viewed as the resumption of normal operation. TO
and
PD
bits are set or cleared differently in different Reset
situations, as indicated in Table 14-2. These bits are
used in software to determine the nature of the Reset.
See Table 14-4 for a full description of Reset states of
all registers.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 14-1.
The MCLR
Reset path has a noise filter to detect and
ignore small pulses. See Section 17.0 “Electrical
Specifications” for pulse-width specifications.
FIGURE 14-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
S
RQ
External
Reset
MCLR/VPP pin
V
DD
OSC1/
WDT
Module
V
DD Rise
Detect
OST/PWRT
LFINTOSC
WDT
Time-out
Power-on Reset
OST
10-bit Ripple Counter
PWRT
Chip_Reset
11-bit Ripple Counter
Reset
Enable OST
Enable PWRT
Sleep
Brown-out
(1)
Reset
SBOREN
BOREN
CLKI pin
Note 1: Refer to the Configuration Word register (Register 14-1).