Datasheet

© 2008 Microchip Technology Inc. DS41262E-page 183
PIC16F631/677/685/687/689/690
13.3 Enabling SPI I/O
To enable the serial port, SSP Enable bit SSPEN of the
SSPCON register must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, re-initialize the
SSPCON registers and then set the SSPEN bit. This
configures the SDI, SDO, SCK and SS
pins as serial
port pins. For the pins to behave as the serial port
function, some must have their data direction bits (in
the TRISB and TRISC registers) appropriately
programmed. That is:
• SDI is automatically controlled by the SPI module
• SDO must have TRISC<7> bit cleared
• SCK (Master mode) must have TRISB<6> bit
cleared
• SCK (Slave mode) must have TRISB<6> bit set
•SS
must have TRISC<6> bit set
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRISB and TRISC) registers to the opposite
value.
13.4 Typical Connection
Figure 13-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their
programmed clock edge and latched on the opposite
edge of the clock. Both processors should be
programmed to the same Clock Polarity (CKP), then
both controllers would send and receive data at the
same time. Whether the data is meaningful (or dummy
data) depends on the application software. This leads
to three scenarios for data transmission:
• Master sends data – Slave sends dummy data
• Master sends data – Slave sends data
• Master sends dummy data – Slave sends data
FIGURE 13-2: SPI MASTER/SLAVE CONNECTION
Serial Input Buffer
(SSPBUF)
Shift Register
(SSPSR)
MSb
LSb
SDO
SDI
Processor 1
SCK
SPI Master SSPM<3:0> = 00xxb
Serial Input Buffer
(SSPBUF)
Shift Register
(SSPSR)
LSb
MSb
SDI
SDO
Processor 2
SCK
SPI Slave SSPM<3:0> = 010xb
Serial Clock