Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller SSOP 20 8-Bit 20 MHz I/O number 18

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Table Of Contents

High-Performance RISC CPU:
Special Microcontroller Features:
Low-Power Features:
Peripheral Features:
PIC16F631 Pin Diagram
- TABLE 1: PIC16F631 Pin Summary
PIC16F677 Pin Diagram
- TABLE 2: PIC16F677 Pin Summary
PIC16F685 Pin Diagram
- TABLE 3: PIC16F685 Pin Summary
PIC16F687/689 Pin Diagram
- TABLE 4: PIC16F687/689 Pin Summary
PIC16F690 Pin Diagram (PDIP, SOIC, SSOP)
- TABLE 5: PIC16F690 Pin Summary
PIC16F631/677/685/687/689/690 Pin Diagram (QFN)
Most Current Data Sheet
Errata
Customer Notification System
1.0 Device Overview
- FIGURE 1-1: PIC16F631 Block Diagram
- FIGURE 1-2: PIC16F677 Block Diagram
- FIGURE 1-3: PIC16F685 Block Diagram
- FIGURE 1-4: PIC16F687/PIC16F689 Block Diagram
- FIGURE 1-5: PIC16F690 Block Diagram
- TABLE 1-1: Pinout Description - PIC16F631
- TABLE 1-2: Pinout Description - PIC16F677
- TABLE 1-3: Pinout Description - PIC16F685
- TABLE 1-4: Pinout Description - PIC16F687/PIC16F689
- TABLE 1-5: Pinout Description - PIC16F690
2.0 Memory Organization
- 2.1 Program Memory Organization
- 2.2 Data Memory Organization
  - 2.2.1 General Purpose Register File
  - 2.2.2 Special Function Registers
- 2.3 PCL and PCLATH
- 2.4 Indirect Addressing, INDF and FSR Registers
  - EXAMPLE 2-1: Indirect Addressing
  - FIGURE 2-10: Direct/Indirect Addressing PIC16F631/677/685/687/689/690
3.0 Oscillator Module (With Fail-Safe Clock Monitor)
- 3.1 Overview
  - FIGURE 3-1: SIMPLIFIED PIC® MCU Clock Source Block Diagram
- 3.2 Oscillator Control
  - Register 3-1: OSCCON: Oscillator Control Register
- 3.3 Clock Source Modes
- 3.4 External Clock Modes
- 3.5 Internal Clock Modes
- 3.6 Clock Switching
  - 3.6.1 System Clock Select (SCS) Bit
  - 3.6.2 Oscillator Start-up Time-out Status (OSTS) Bit
- 3.7 Two-Speed Clock Start-up Mode
- 3.8 Fail-Safe Clock Monitor
4.0 I/O Ports
- 4.1 PORTA and the TRISA Registers
- 4.2 Additional Pin Functions
- 4.3 PORTB and TRISB Registers
  - EXAMPLE 4-3: Initializing PORTB
- 4.4 Additional PORTB Pin Functions
- 4.5 PORTC and TRISC Registers
5.0 Timer0 Module
- 5.1 Timer0 Operation
6.0 Timer1 Module with Gate Control
- 6.1 Timer1 Operation
- 6.2 Clock Source Selection
- 6.3 Timer1 Prescaler
- 6.4 Timer1 Oscillator
- 6.5 Timer1 Operation in Asynchronous Counter Mode
  - 6.5.1 Reading and Writing Timer1 in Asynchronous Counter Mode
- 6.6 Timer1 Gate
- 6.7 Timer1 Interrupt
- 6.8 Timer1 Operation During Sleep
- 6.9 ECCP Capture/Compare Time Base
- 6.10 ECCP Special Event Trigger
- 6.11 Comparator Synchronization
  - FIGURE 6-2: Timer1 Incrementing Edge
- 6.12 Timer1 Control Register
  - Register 6-1: T1CON: Timer 1 Control Register
  - TABLE 6-1: Summary of Registers Associated with Timer1
7.0 Timer2 Module
- 7.1 Timer2 Operation
8.0 Comparator Module
- 8.1 Comparator Overview
- 8.2 Comparator Control
- 8.3 Comparator Response Time
- 8.4 Comparator Interrupt Operation
  - FIGURE 8-4: Comparator Interrupt Timing W/O CMxCON0 Read
  - FIGURE 8-5: Comparator Interrupt Timing With CMxCON0 Read
- 8.5 Operation During Sleep
- 8.6 Effects of a Reset
  - Register 8-1: CM1CON0: COMPARATOR C1 CONTROL REGISTER 0
  - Register 8-2: CM2CON0: COMPARATOR C2 CONTROL REGISTER 0
- 8.7 Analog Input Connection Considerations
  - FIGURE 8-6: Analog Input Model
- 8.8 Additional Comparator Features
- 8.9 Comparator SR Latch
  - 8.9.1 Latch Operation
  - 8.9.2 Latch Output
    - FIGURE 8-7: SR Latch Simplified Block Diagram
    - Register 8-4: SRCON: SR Latch Control Register
- 8.10 Comparator Voltage Reference
9.0 Analog-to-Digital Converter (ADC) Module
- FIGURE 9-1: ADC Block Diagram
- 9.1 ADC Configuration
- 9.2 ADC Operation
- 9.3 A/D Acquisition Requirements
10.0 Data EEPROM and Flash Program Memory Control
- 10.1 EEADR and EEADRH Registers
- 10.2 Write Verify
  - EXAMPLE 10-4: Write Verify
  - 10.2.1 Using the Data EEPROM
- 10.3 Protection Against Spurious Write
- 10.4 Data EEPROM Operation During Code-Protect
  - TABLE 10-1: Summary of Registers Associated with Data EEPROM
11.0 Enhanced Capture/Compare/PWM Module
- TABLE 11-1: ECCP Mode - Timer Resources Required
- Register 11-1: CCP1CON: Enhanced CCP1 Control Register
- 11.1 Capture Mode
- 11.2 Compare Mode
- 11.3 PWM Mode
- 11.4 PWM (Enhanced Mode)
12.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)
- FIGURE 12-1: EUSART Transmit Block Diagram
- FIGURE 12-2: EUSART Receive Block Diagram
- 12.1 EUSART Asynchronous Mode
  - 12.1.1 EUSART Asynchronous Transmitter
  - 12.1.2 EUSART Asynchronous Receiver
    - FIGURE 12-5: Asynchronous Reception
    - TABLE 12-2: Registers Associated with Asynchronous Reception
- 12.2 Clock Accuracy with Asynchronous Operation
- 12.3 EUSART Baud Rate Generator (BRG)
- 12.4 EUSART Synchronous Mode
  - 12.4.1 Synchronous Master Mode
  - 12.4.2 Synchronous slave Mode
    - TABLE 12-9: Registers Associated with Synchronous Slave Transmission
    - TABLE 12-10: Registers Associated with Synchronous Slave Reception
- 12.5 EUSART Operation During Sleep
  - 12.5.1 Synchronous Receive During Sleep
  - 12.5.2 Synchronous Transmit During Sleep
13.0 SSP Module Overview
- 13.1 SPI Mode
- 13.2 Operation
  - EXAMPLE 13-1: Loading the SSPBUF (SSPSR) Register
- 13.3 Enabling SPI I/O
- 13.4 Typical Connection
  - FIGURE 13-2: SPI Master/Slave Connection
- 13.5 Master Mode
  - FIGURE 13-3: SPI Mode Waveform (Master Mode)
- 13.6 Slave Mode
- 13.7 Slave Select Synchronization
- 13.8 Sleep Operation
- 13.9 Effects of a Reset
- 13.10 Bus Mode Compatibility
  - TABLE 13-1: SPI Bus Modes
  - TABLE 13-2: Registers Associated with SPI Operation(1)
- 13.11 SSP I2C Operation
  - FIGURE 13-7: SSP Block Diagram (I2C™ Mode)
- 13.12 Slave Mode
- 13.13 Master Mode
- 13.14 Multi-Master Mode
  - 13.14.1 Clock Synchronization and the CKP Bit
    - FIGURE 13-12: Clock Synchronization Timing
    - TABLE 13-4: Registers Associated with I2C™ Operation(1)
14.0 Special Features of the CPU
- 14.1 Configuration Bits
  - Register 14-1: CONFIG: Configuration Word Register
- 14.2 Reset
- 14.3 Interrupts
- 14.4 Context Saving During Interrupts
  - EXAMPLE 14-1: Saving STATUS and W Registers in RAM
- 14.5 Watchdog Timer (WDT)
  - 14.5.1 WDT Oscillator
  - 14.5.2 WDT Control
- 14.6 Power-Down Mode (Sleep)
  - 14.6.1 Wake-up from Sleep
  - 14.6.2 Wake-up Using Interrupts
    - FIGURE 14-10: Wake-up from Sleep Through Interrupt
- 14.7 Code Protection
- 14.8 ID Locations
- 14.9 In-Circuit Serial Programming
  - FIGURE 14-11: Typical In-Circuit Serial Programming Connection
15.0 Instruction Set Summary
- 15.1 Read-Modify-Write Operations
- 15.2 Instruction Descriptions
16.0 Development Support
- 16.1 MPLAB Integrated Development Environment Software
- 16.2 MPASM Assembler
- 16.3 MPLAB C18 and MPLAB C30 C Compilers
- 16.4 MPLINK Object Linker/ MPLIB Object Librarian
- 16.5 MPLAB ASM30 Assembler, Linker and Librarian
- 16.6 MPLAB SIM Software Simulator
- 16.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator
- 16.8 MPLAB REAL ICE In-Circuit Emulator System
- 16.9 MPLAB ICD 2 In-Circuit Debugger
- 16.10 MPLAB PM3 Device Programmer
- 16.11 PICSTART Plus Development Programmer
- 16.12 PICkit 2 Development Programmer
- 16.13 Demonstration, Development and Evaluation Boards
17.0 Electrical Specifications
- Absolute Maximum Ratings(†)
  - FIGURE 17-1: PIC16F631/677/685/687/689/690 Voltage-Frequency Graph, -40˚C £ ta £ +125˚C
  - FIGURE 17-2: HFINTOSC Frequency Accuracy Over Device Vdd and Temperature
- 17.1 DC Characteristics: PIC16F631/677/685/687/689/690-I (Industrial) PIC16F631/677/685/687/689/690-E (Extended)
- 17.2 DC Characteristics: PIC16F631/677/685/687/689/690-I (Industrial) PIC16F631/677/685/687/689/690-E (Extended)
- 17.3 DC Characteristics: PIC16F631/677/685/687/689/690-E (Extended)
- 17.4 DC Characteristics: PIC16F631/677/685/687/689/690-I (Industrial) PIC16F631/677/685/687/689/690-E (Extended)
- 17.5 Thermal Considerations
- 17.6 Timing Parameter Symbology
  - FIGURE 17-3: Load Conditions
- 17.7 AC Characteristics: PIC16F631/677/685/687/689/690 (Industrial, Extended)
18.0 DC and AC Characteristics Graphs and Tables
- FIGURE 18-1: Typical Idd vs. Fosc Over Vdd (EC Mode)
- FIGURE 18-2: Maximum Idd vs. Fosc Over Vdd (EC Mode)
- FIGURE 18-3: Typical Idd vs. Fosc Over Vdd (HS Mode)
- FIGURE 18-4: Maximum Idd vs. Fosc Over Vdd (HS Mode)
- FIGURE 18-5: Typical Idd vs. Vdd Over Fosc (XT Mode)
- FIGURE 18-6: Maximum Idd vs. Vdd Over Fosc (XT Mode)
- FIGURE 18-7: Idd vs. Vdd (LP Mode)
- FIGURE 18-8: Typical Idd vs. Vdd Over Fosc (EXTRC Mode)
- FIGURE 18-9: Maximum Idd vs. Vdd Over Fosc (EXTRC Mode)
- FIGURE 18-10: Idd vs. Vdd Over Fosc (LFINTOSC Mode, 31 kHz)
- FIGURE 18-11: Typical Idd vs. Fosc Over Vdd (HFINTOSC Mode)
- FIGURE 18-12: Maximum Idd vs. Fosc Over Vdd (HFINTOSC Mode)
- FIGURE 18-13: Typical Ipd vs. Vdd (Sleep Mode, all Peripherals Disabled)
- FIGURE 18-14: Maximum Ipd vs. Vdd (Sleep Mode, all Peripherals Disabled)
- FIGURE 18-15: Comparator Ipd vs. Vdd (Both Comparators Enabled)
- FIGURE 18-16: BOR Ipd VS. Vdd Over Temperature
- FIGURE 18-17: Typical WDT Ipd VS. Vdd Over Temperature
- FIGURE 18-18: Maximum WDT Ipd VS. Vdd Over Temperature
- FIGURE 18-19: WDT Period VS. Vdd Over Temperature
- FIGURE 18-20: WDT Period VS. Temperature Over Vdd (5.0V)
- FIGURE 18-21: CVref Ipd VS. Vdd Over Temperature (High Range)
- FIGURE 18-22: CVref Ipd VS. Vdd Over Temperature (Low Range)
- FIGURE 18-23: Typical VP6 Reference Ipd vs. Vdd (25C)
- FIGURE 18-24: Maximum VP6 Reference Ipd vs. Vdd Over Temperature
- FIGURE 18-25: T1OSC Ipd vs. Vdd Over Temperature (32 kHz)
- FIGURE 18-26: Vol VS. Iol Over Temperature (Vdd = 3.0V)
- FIGURE 18-27: Vol VS. Iol Over Temperature (Vdd = 5.0V)
- FIGURE 18-28: Voh VS. Ioh Over Temperature (Vdd = 3.0V)
- FIGURE 18-29: Voh VS. Ioh Over Temperature (Vdd = 5.0V)
- FIGURE 18-30: TTL Input Threshold Vin VS. Vdd Over Temperature
- FIGURE 18-31: Schmitt Trigger Input Threshold Vin VS. Vdd Over Temperature
- FIGURE 18-32: Comparator Response Time (Rising Edge)
- FIGURE 18-33: Comparator Response Time (Falling Edge)
- FIGURE 18-34: LFINTOSC Frequency vs. Vdd Over Temperature (31 kHz)
- FIGURE 18-35: ADC Clock Period vs. Vdd Over Temperature
- FIGURE 18-36: Typical HFINTOSC Start-Up Times vs. Vdd Over Temperature
- FIGURE 18-37: Maximum HFINTOSC Start-Up Times vs. Vdd Over Temperature
- FIGURE 18-38: Minimum HFINTOSC Start-Up Times vs. Vdd Over Temperature
- FIGURE 18-39: Typical HFINTOSC Frequency Change vs. Vdd (25C)
- FIGURE 18-40: Typical HFINTOSC Frequency Change Over Device Vdd (85C)
- FIGURE 18-41: Typical HFINTOSC Frequency Change vs. Vdd (125C)
- FIGURE 18-42: Typical HFINTOSC Frequency Change vs. Vdd (-40C)
- FIGURE 18-43: Typical VP6 Reference Voltage vs. Vdd (25C)
- FIGURE 18-44: Typical VP6 Reference Voltage Over Temperature (3V)
- FIGURE 18-45: Typical VP6 Reference Voltage Over Temperature (5V)
- FIGURE 18-46: Typical VP6 Reference Voltage Distribution (3V, 25C)
- FIGURE 18-47: Typical VP6 Reference Voltage Distribution (3V, 85C)
- FIGURE 18-48: Typical VP6 Reference Voltage Distribution (3V, 125C)
- FIGURE 18-49: Typical VP6 Reference Voltage Distribution (3V, -40C)
- FIGURE 18-50: Typical VP6 Reference Voltage Distribution (5V, 25C)
- FIGURE 18-51: Typical VP6 Reference Voltage Distribution (5V, 85C)
- FIGURE 18-52: Typical VP6 Reference Voltage Distribution (5V, 125C)
- FIGURE 18-53: Typical VP6 Reference Voltage Distribution (5V, -40C)
19.0 Packaging Information
- 19.1 Package Marking Information
- 19.2 Package Details
Appendix A: Data Sheet Revision History
- Revision A (March 2005)
- Revision B (May 2006)
- Revision C (July 2006)
- Revision D (February 2007)
- Revision E (March 2008)
Appendix B: Migrating from other PIC® Devices
- TABLE B-1: feature comparison
INDEX
The Microchip Web Site
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Reader Response
Product Identification System
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PIC16F631/677/685/687/689/690

TABLE 12-2: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

NameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0

Value on

POR, BOR

Value on

all other

Resets

BAUDCTL

ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00

INTCON GIE PEIE

T0IE INTE RABIE T0IF INTF RABIF 0000 000x 0000 000x

PIE1

— ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000

PIR1

— ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000

RCREG EUSART Receive Data Register 0000 0000 0000 0000

RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x

SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000

SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000

TRISB

TRISB7 TRISB6 TRISB5 TRISB4 1111 ---- 1111 ----

TXREG

EUSART Transmit Data Register 0000 0000 0000 0000

TXSTA

CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010

Legend: x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Asynchronous Reception.