Datasheet

PIC16F631/677/685/687/689/690
DS41262E-page 132 © 2008 Microchip Technology Inc.
11.3.4 OPERATION IN SLEEP MODE
In Sleep mode, the TMR2 register will not increment
and the state of the module will not change. If the CCP1
pin is driving a value, it will continue to drive that value.
When the device wakes up, TMR2 will continue from its
previous state.
11.3.5 CHANGES IN SYSTEM CLOCK
FREQUENCY
The PWM frequency is derived from the system clock
frequency. Any changes in the system clock frequency
will result in changes to the PWM frequency. See
Section 3.0 “Oscillator Module (With Fail-Safe
Clock Monitor)” for additional details.
11.3.6 EFFECTS OF RESET
Any Reset will force all ports to Input mode and the
CCP registers to their Reset states.
11.3.7 SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1. Disable the PWM pin (CCP1) output driver by
setting the associated TRIS bit.
2. Set the PWM period by loading the PR2 register.
3. Configure the CCP module for the PWM mode
by loading the CCP1CON register with the
appropriate values.
4. Set the PWM duty cycle by loading the CCPR1L
register and DC1B<1:0> bits of the CCP1CON
register.
5. Configure and start Timer2:
• Clear the TMR2IF interrupt flag bit of the
PIR1 register.
• Set the Timer2 prescale value by loading the
T2CKPS bits of the T2CON register.
• Enable Timer2 by setting the TMR2ON bit of
the T2CON register.
6. Enable PWM output after a new PWM cycle has
started:
• Wait until Timer2 overflows (TMR2IF bit of
the PIR1 register is set).
• Enable the CCP1 pin output driver by clearing
the associated TRIS bit.
11.4 PWM (Enhanced Mode)
The Enhanced PWM Mode can generate a PWM signal
on up to four different output pins with up to 10-bits of
resolution. It can do this through four different PWM
Output modes:
• Single PWM
• Half-Bridge PWM
• Full-Bridge PWM, Forward mode
• Full-Bridge PWM, Reverse mode
To select an Enhanced PWM mode, the P1M bits of the
CCP1CON register must be set appropriately.
The PWM outputs are multiplexed with I/O pins and are
designated P1A, P1B, P1C and P1D. The polarity of the
PWM pins is configurable and is selected by setting the
CCP1M bits in the CCP1CON register appropriately.
Table 11-4 shows the pin assignments for each
Enhanced PWM mode.
Figure 11-5 shows an example of a simplified block
diagram of the Enhanced PWM module.
Note: To prevent the generation of an
incomplete waveform when the PWM is
first enabled, the ECCP module waits until
the start of a new PWM period before
generating a PWM signal.