Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller SSOP 20 8-Bit 20 MHz I/O number 18

Table Of Contents

High-Performance RISC CPU:
Special Microcontroller Features:
Low-Power Features:
Peripheral Features:
PIC16F631 Pin Diagram
- TABLE 1: PIC16F631 Pin Summary
PIC16F677 Pin Diagram
- TABLE 2: PIC16F677 Pin Summary
PIC16F685 Pin Diagram
- TABLE 3: PIC16F685 Pin Summary
PIC16F687/689 Pin Diagram
- TABLE 4: PIC16F687/689 Pin Summary
PIC16F690 Pin Diagram (PDIP, SOIC, SSOP)
- TABLE 5: PIC16F690 Pin Summary
PIC16F631/677/685/687/689/690 Pin Diagram (QFN)
Most Current Data Sheet
Errata
Customer Notification System
1.0 Device Overview
- FIGURE 1-1: PIC16F631 Block Diagram
- FIGURE 1-2: PIC16F677 Block Diagram
- FIGURE 1-3: PIC16F685 Block Diagram
- FIGURE 1-4: PIC16F687/PIC16F689 Block Diagram
- FIGURE 1-5: PIC16F690 Block Diagram
- TABLE 1-1: Pinout Description - PIC16F631
- TABLE 1-2: Pinout Description - PIC16F677
- TABLE 1-3: Pinout Description - PIC16F685
- TABLE 1-4: Pinout Description - PIC16F687/PIC16F689
- TABLE 1-5: Pinout Description - PIC16F690
2.0 Memory Organization
- 2.1 Program Memory Organization
- 2.2 Data Memory Organization
  - 2.2.1 General Purpose Register File
  - 2.2.2 Special Function Registers
- 2.3 PCL and PCLATH
- 2.4 Indirect Addressing, INDF and FSR Registers
  - EXAMPLE 2-1: Indirect Addressing
  - FIGURE 2-10: Direct/Indirect Addressing PIC16F631/677/685/687/689/690
3.0 Oscillator Module (With Fail-Safe Clock Monitor)
- 3.1 Overview
  - FIGURE 3-1: SIMPLIFIED PIC® MCU Clock Source Block Diagram
- 3.2 Oscillator Control
  - Register 3-1: OSCCON: Oscillator Control Register
- 3.3 Clock Source Modes
- 3.4 External Clock Modes
- 3.5 Internal Clock Modes
- 3.6 Clock Switching
  - 3.6.1 System Clock Select (SCS) Bit
  - 3.6.2 Oscillator Start-up Time-out Status (OSTS) Bit
- 3.7 Two-Speed Clock Start-up Mode
- 3.8 Fail-Safe Clock Monitor
4.0 I/O Ports
- 4.1 PORTA and the TRISA Registers
- 4.2 Additional Pin Functions
- 4.3 PORTB and TRISB Registers
  - EXAMPLE 4-3: Initializing PORTB
- 4.4 Additional PORTB Pin Functions
- 4.5 PORTC and TRISC Registers
5.0 Timer0 Module
- 5.1 Timer0 Operation
6.0 Timer1 Module with Gate Control
- 6.1 Timer1 Operation
- 6.2 Clock Source Selection
- 6.3 Timer1 Prescaler
- 6.4 Timer1 Oscillator
- 6.5 Timer1 Operation in Asynchronous Counter Mode
  - 6.5.1 Reading and Writing Timer1 in Asynchronous Counter Mode
- 6.6 Timer1 Gate
- 6.7 Timer1 Interrupt
- 6.8 Timer1 Operation During Sleep
- 6.9 ECCP Capture/Compare Time Base
- 6.10 ECCP Special Event Trigger
- 6.11 Comparator Synchronization
  - FIGURE 6-2: Timer1 Incrementing Edge
- 6.12 Timer1 Control Register
  - Register 6-1: T1CON: Timer 1 Control Register
  - TABLE 6-1: Summary of Registers Associated with Timer1
7.0 Timer2 Module
- 7.1 Timer2 Operation
8.0 Comparator Module
- 8.1 Comparator Overview
- 8.2 Comparator Control
- 8.3 Comparator Response Time
- 8.4 Comparator Interrupt Operation
  - FIGURE 8-4: Comparator Interrupt Timing W/O CMxCON0 Read
  - FIGURE 8-5: Comparator Interrupt Timing With CMxCON0 Read
- 8.5 Operation During Sleep
- 8.6 Effects of a Reset
  - Register 8-1: CM1CON0: COMPARATOR C1 CONTROL REGISTER 0
  - Register 8-2: CM2CON0: COMPARATOR C2 CONTROL REGISTER 0
- 8.7 Analog Input Connection Considerations
  - FIGURE 8-6: Analog Input Model
- 8.8 Additional Comparator Features
- 8.9 Comparator SR Latch
  - 8.9.1 Latch Operation
  - 8.9.2 Latch Output
    - FIGURE 8-7: SR Latch Simplified Block Diagram
    - Register 8-4: SRCON: SR Latch Control Register
- 8.10 Comparator Voltage Reference
9.0 Analog-to-Digital Converter (ADC) Module
- FIGURE 9-1: ADC Block Diagram
- 9.1 ADC Configuration
- 9.2 ADC Operation
- 9.3 A/D Acquisition Requirements
10.0 Data EEPROM and Flash Program Memory Control
- 10.1 EEADR and EEADRH Registers
- 10.2 Write Verify
  - EXAMPLE 10-4: Write Verify
  - 10.2.1 Using the Data EEPROM
- 10.3 Protection Against Spurious Write
- 10.4 Data EEPROM Operation During Code-Protect
  - TABLE 10-1: Summary of Registers Associated with Data EEPROM
11.0 Enhanced Capture/Compare/PWM Module
- TABLE 11-1: ECCP Mode - Timer Resources Required
- Register 11-1: CCP1CON: Enhanced CCP1 Control Register
- 11.1 Capture Mode
- 11.2 Compare Mode
- 11.3 PWM Mode
- 11.4 PWM (Enhanced Mode)
12.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)
- FIGURE 12-1: EUSART Transmit Block Diagram
- FIGURE 12-2: EUSART Receive Block Diagram
- 12.1 EUSART Asynchronous Mode
  - 12.1.1 EUSART Asynchronous Transmitter
  - 12.1.2 EUSART Asynchronous Receiver
    - FIGURE 12-5: Asynchronous Reception
    - TABLE 12-2: Registers Associated with Asynchronous Reception
- 12.2 Clock Accuracy with Asynchronous Operation
- 12.3 EUSART Baud Rate Generator (BRG)
- 12.4 EUSART Synchronous Mode
  - 12.4.1 Synchronous Master Mode
  - 12.4.2 Synchronous slave Mode
    - TABLE 12-9: Registers Associated with Synchronous Slave Transmission
    - TABLE 12-10: Registers Associated with Synchronous Slave Reception
- 12.5 EUSART Operation During Sleep
  - 12.5.1 Synchronous Receive During Sleep
  - 12.5.2 Synchronous Transmit During Sleep
13.0 SSP Module Overview
- 13.1 SPI Mode
- 13.2 Operation
  - EXAMPLE 13-1: Loading the SSPBUF (SSPSR) Register
- 13.3 Enabling SPI I/O
- 13.4 Typical Connection
  - FIGURE 13-2: SPI Master/Slave Connection
- 13.5 Master Mode
  - FIGURE 13-3: SPI Mode Waveform (Master Mode)
- 13.6 Slave Mode
- 13.7 Slave Select Synchronization
- 13.8 Sleep Operation
- 13.9 Effects of a Reset
- 13.10 Bus Mode Compatibility
  - TABLE 13-1: SPI Bus Modes
  - TABLE 13-2: Registers Associated with SPI Operation(1)
- 13.11 SSP I2C Operation
  - FIGURE 13-7: SSP Block Diagram (I2C™ Mode)
- 13.12 Slave Mode
- 13.13 Master Mode
- 13.14 Multi-Master Mode
  - 13.14.1 Clock Synchronization and the CKP Bit
    - FIGURE 13-12: Clock Synchronization Timing
    - TABLE 13-4: Registers Associated with I2C™ Operation(1)
14.0 Special Features of the CPU
- 14.1 Configuration Bits
  - Register 14-1: CONFIG: Configuration Word Register
- 14.2 Reset
- 14.3 Interrupts
- 14.4 Context Saving During Interrupts
  - EXAMPLE 14-1: Saving STATUS and W Registers in RAM
- 14.5 Watchdog Timer (WDT)
  - 14.5.1 WDT Oscillator
  - 14.5.2 WDT Control
- 14.6 Power-Down Mode (Sleep)
  - 14.6.1 Wake-up from Sleep
  - 14.6.2 Wake-up Using Interrupts
    - FIGURE 14-10: Wake-up from Sleep Through Interrupt
- 14.7 Code Protection
- 14.8 ID Locations
- 14.9 In-Circuit Serial Programming
  - FIGURE 14-11: Typical In-Circuit Serial Programming Connection
15.0 Instruction Set Summary
- 15.1 Read-Modify-Write Operations
- 15.2 Instruction Descriptions
16.0 Development Support
- 16.1 MPLAB Integrated Development Environment Software
- 16.2 MPASM Assembler
- 16.3 MPLAB C18 and MPLAB C30 C Compilers
- 16.4 MPLINK Object Linker/ MPLIB Object Librarian
- 16.5 MPLAB ASM30 Assembler, Linker and Librarian
- 16.6 MPLAB SIM Software Simulator
- 16.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator
- 16.8 MPLAB REAL ICE In-Circuit Emulator System
- 16.9 MPLAB ICD 2 In-Circuit Debugger
- 16.10 MPLAB PM3 Device Programmer
- 16.11 PICSTART Plus Development Programmer
- 16.12 PICkit 2 Development Programmer
- 16.13 Demonstration, Development and Evaluation Boards
17.0 Electrical Specifications
- Absolute Maximum Ratings(†)
  - FIGURE 17-1: PIC16F631/677/685/687/689/690 Voltage-Frequency Graph, -40˚C £ ta £ +125˚C
  - FIGURE 17-2: HFINTOSC Frequency Accuracy Over Device Vdd and Temperature
- 17.1 DC Characteristics: PIC16F631/677/685/687/689/690-I (Industrial) PIC16F631/677/685/687/689/690-E (Extended)
- 17.2 DC Characteristics: PIC16F631/677/685/687/689/690-I (Industrial) PIC16F631/677/685/687/689/690-E (Extended)
- 17.3 DC Characteristics: PIC16F631/677/685/687/689/690-E (Extended)
- 17.4 DC Characteristics: PIC16F631/677/685/687/689/690-I (Industrial) PIC16F631/677/685/687/689/690-E (Extended)
- 17.5 Thermal Considerations
- 17.6 Timing Parameter Symbology
  - FIGURE 17-3: Load Conditions
- 17.7 AC Characteristics: PIC16F631/677/685/687/689/690 (Industrial, Extended)
18.0 DC and AC Characteristics Graphs and Tables
- FIGURE 18-1: Typical Idd vs. Fosc Over Vdd (EC Mode)
- FIGURE 18-2: Maximum Idd vs. Fosc Over Vdd (EC Mode)
- FIGURE 18-3: Typical Idd vs. Fosc Over Vdd (HS Mode)
- FIGURE 18-4: Maximum Idd vs. Fosc Over Vdd (HS Mode)
- FIGURE 18-5: Typical Idd vs. Vdd Over Fosc (XT Mode)
- FIGURE 18-6: Maximum Idd vs. Vdd Over Fosc (XT Mode)
- FIGURE 18-7: Idd vs. Vdd (LP Mode)
- FIGURE 18-8: Typical Idd vs. Vdd Over Fosc (EXTRC Mode)
- FIGURE 18-9: Maximum Idd vs. Vdd Over Fosc (EXTRC Mode)
- FIGURE 18-10: Idd vs. Vdd Over Fosc (LFINTOSC Mode, 31 kHz)
- FIGURE 18-11: Typical Idd vs. Fosc Over Vdd (HFINTOSC Mode)
- FIGURE 18-12: Maximum Idd vs. Fosc Over Vdd (HFINTOSC Mode)
- FIGURE 18-13: Typical Ipd vs. Vdd (Sleep Mode, all Peripherals Disabled)
- FIGURE 18-14: Maximum Ipd vs. Vdd (Sleep Mode, all Peripherals Disabled)
- FIGURE 18-15: Comparator Ipd vs. Vdd (Both Comparators Enabled)
- FIGURE 18-16: BOR Ipd VS. Vdd Over Temperature
- FIGURE 18-17: Typical WDT Ipd VS. Vdd Over Temperature
- FIGURE 18-18: Maximum WDT Ipd VS. Vdd Over Temperature
- FIGURE 18-19: WDT Period VS. Vdd Over Temperature
- FIGURE 18-20: WDT Period VS. Temperature Over Vdd (5.0V)
- FIGURE 18-21: CVref Ipd VS. Vdd Over Temperature (High Range)
- FIGURE 18-22: CVref Ipd VS. Vdd Over Temperature (Low Range)
- FIGURE 18-23: Typical VP6 Reference Ipd vs. Vdd (25C)
- FIGURE 18-24: Maximum VP6 Reference Ipd vs. Vdd Over Temperature
- FIGURE 18-25: T1OSC Ipd vs. Vdd Over Temperature (32 kHz)
- FIGURE 18-26: Vol VS. Iol Over Temperature (Vdd = 3.0V)
- FIGURE 18-27: Vol VS. Iol Over Temperature (Vdd = 5.0V)
- FIGURE 18-28: Voh VS. Ioh Over Temperature (Vdd = 3.0V)
- FIGURE 18-29: Voh VS. Ioh Over Temperature (Vdd = 5.0V)
- FIGURE 18-30: TTL Input Threshold Vin VS. Vdd Over Temperature
- FIGURE 18-31: Schmitt Trigger Input Threshold Vin VS. Vdd Over Temperature
- FIGURE 18-32: Comparator Response Time (Rising Edge)
- FIGURE 18-33: Comparator Response Time (Falling Edge)
- FIGURE 18-34: LFINTOSC Frequency vs. Vdd Over Temperature (31 kHz)
- FIGURE 18-35: ADC Clock Period vs. Vdd Over Temperature
- FIGURE 18-36: Typical HFINTOSC Start-Up Times vs. Vdd Over Temperature
- FIGURE 18-37: Maximum HFINTOSC Start-Up Times vs. Vdd Over Temperature
- FIGURE 18-38: Minimum HFINTOSC Start-Up Times vs. Vdd Over Temperature
- FIGURE 18-39: Typical HFINTOSC Frequency Change vs. Vdd (25C)
- FIGURE 18-40: Typical HFINTOSC Frequency Change Over Device Vdd (85C)
- FIGURE 18-41: Typical HFINTOSC Frequency Change vs. Vdd (125C)
- FIGURE 18-42: Typical HFINTOSC Frequency Change vs. Vdd (-40C)
- FIGURE 18-43: Typical VP6 Reference Voltage vs. Vdd (25C)
- FIGURE 18-44: Typical VP6 Reference Voltage Over Temperature (3V)
- FIGURE 18-45: Typical VP6 Reference Voltage Over Temperature (5V)
- FIGURE 18-46: Typical VP6 Reference Voltage Distribution (3V, 25C)
- FIGURE 18-47: Typical VP6 Reference Voltage Distribution (3V, 85C)
- FIGURE 18-48: Typical VP6 Reference Voltage Distribution (3V, 125C)
- FIGURE 18-49: Typical VP6 Reference Voltage Distribution (3V, -40C)
- FIGURE 18-50: Typical VP6 Reference Voltage Distribution (5V, 25C)
- FIGURE 18-51: Typical VP6 Reference Voltage Distribution (5V, 85C)
- FIGURE 18-52: Typical VP6 Reference Voltage Distribution (5V, 125C)
- FIGURE 18-53: Typical VP6 Reference Voltage Distribution (5V, -40C)
19.0 Packaging Information
- 19.1 Package Marking Information
- 19.2 Package Details
Appendix A: Data Sheet Revision History
- Revision A (March 2005)
- Revision B (May 2006)
- Revision C (July 2006)
- Revision D (February 2007)
- Revision E (March 2008)
Appendix B: Migrating from other PIC® Devices
- TABLE B-1: feature comparison
INDEX
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PIC16F631/677/685/687/689/690

Data Sheet

20-Pin Flash-Based, 8-Bit

CMOS Microcontrollers with

nanoWatt Technology

Summary of content (306 pages)

PAGE 1
PIC16F631/677/685/687/689/690 Data Sheet 20-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology © 2008 Microchip Technology Inc.
PAGE 2
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 3
PIC16F631/677/685/687/689/690 20-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology High-Performance RISC CPU: Low-Power Features: • Only 35 Instructions to Learn: - All single-cycle instructions except branches • Operating Speed: - DC – 20 MHz oscillator/clock input - DC – 200 ns instruction cycle • Interrupt Capability • 8-Level Deep Hardware Stack • Direct, Indirect and Relative Addressing modes • Standby Current: - 50 nA @ 2.0V, typical • Operating Current: - 11 μA @ 32 kHz, 2.
PAGE 4
PIC16F631/677/685/687/689/690 Device Program Memory Data Memory Flash (words) SRAM EEPROM (bytes) (bytes) PIC16F631 PIC16F677 PIC16F685 PIC16F687 PIC16F689 PIC16F690 1024 2048 4096 2048 4096 4096 64 128 256 128 256 256 I/O 128 256 256 256 256 256 10-bit A/D Comparators (ch) 18 18 18 18 18 18 — 12 12 12 12 12 2 2 2 2 2 2 Timers 8/16-bit SSP ECCP+ EUSART 1/1 1/1 2/1 1/1 1/1 2/1 No Yes No Yes Yes Yes No No Yes No No Yes No No No Yes Yes Yes PIC16F631 Pin Diagram VDD RA5/T1CKI/OSC1/CLKIN R
PAGE 5
PIC16F631/677/685/687/689/690 PIC16F677 Pin Diagram VDD RA5/T1CKI/OSC1/CLKIN RA4/AN3/T1G/OSC2/CLKOUT RA3/MCLR/VPP RC5 RC4/C2OUT RC3/AN7C12IN3RC6/AN8/SS RC7/AN9/SDO RB7 TABLE 2: 1 2 3 4 5 6 7 8 9 10 PIC16F677 20-pin PDIP, SOIC, SSOP 20 19 18 17 16 15 14 13 12 11 VSS RA0/AN0/C1IN+/ICSPDAT/ULPWU RA1/AN1/C12IN0-/VREF/ICSPCLK RA2/AN2/T0CKI/INT/C1OUT RC0/AN4/C2IN+ RC1/AN5/C12IN1RC2/AN6/C12IN2RB4/AN10/SDI/SDA RB5/AN11 RB6/SCK/SCL PIC16F677 PIN SUMMARY I/O Pin Analog Comparators Timers SSP Interrupt
PAGE 6
PIC16F631/677/685/687/689/690 PIC16F685 Pin Diagram VDD RA5/T1CKI/OSC1/CLKIN RA4/AN3/T1G/OSC2/CLKOUT RA3/MCLR/VPP RC5/CCP1/P1A RC4/C2OUT/P1B RC3/AN7/C12IN3-/P1C RC6/AN8 RC7/AN9 RB7 TABLE 3: 1 2 3 4 5 6 7 8 9 10 PIC16F685 20-pin PDIP, SOIC, SSOP 20 19 18 17 16 15 14 13 12 11 VSS RA0/AN0/C1IN+/ICSPDAT/ULPWU RA1/AN1/C12IN0-/VREF/ICSPCLK RA2/AN2/T0CKI/INT/C1OUT RC0/AN4/C2IN+ RC1/AN5/C12IN1RC2/AN6/C12IN2-/P1D RB4/AN10 RB5/AN11 RB6 PIC16F685 PIN SUMMARY I/O Pin Analog Comparators Timers ECCP Interru
PAGE 7
PIC16F631/677/685/687/689/690 PIC16F687/689 Pin Diagram VDD RA5/T1CKI/OSC1/CLKIN RA4/AN3/T1G/OSC2/CLKOUT RA3/MCLR/VPP RC5 RC4/C2OUT RC3/AN7/C12IN3RC6/AN8/SS RC7/AN9/SDO RB7/TX/CK TABLE 4: 1 2 3 4 5 6 7 8 9 10 PIC16F687/689 20-pin PDIP, SOIC, SSOP 20 19 18 17 16 15 14 13 12 11 VSS RA0/AN0/C1IN+/ICSPDAT/ULPWU RA1/AN1/C12IN0-/VREF/ICSPCLK RA2/AN2/T0CKI/INT/C1OUT RC0/AN4/C2IN+ RC1/AN5/C12IN1RC2/AN6/C12IN2RB4/AN10/SDI/SDA RB5/AN11/RX/DT RB6/SCK/SCL PIC16F687/689 PIN SUMMARY I/O Pin Analog Comparators
PAGE 8
PIC16F631/677/685/687/689/690 PIC16F690 Pin Diagram (PDIP, SOIC, SSOP) VDD RA5/T1CKI/OSC1/CLKIN RA4/AN3/T1G/OSC2/CLKOUT RA3/MCLR/VPP RC5/CCP1/P1A RC4/C2OUT/P1B RC3/AN7/C12IN3-/P1C RC6/AN8/SS RC7/AN9/SDO RB7/TX/CK TABLE 5: I/O 1 2 3 4 5 6 7 8 9 10 PIC16F690 20-pin PDIP, SOIC, SSOP 20 19 18 17 16 15 14 13 12 11 VSS RA0/AN0/C1IN+/ICSPDAT/ULPWU RA1/AN1/C12IN0-/VREF/ICSPCLK RA2/AN2/T0CKI/INT/C1OUT RC0/AN4/C2IN+ RC1/AN5/C12IN1RC2/AN6/C12IN2-/P1D RB4/AN10/SDI/SDA RB5/AN11/RX/DT RB6/SCK/SCL PIC16F690 PIN SUM
PAGE 9
PIC16F631/677/685/687/689/690 PIC16F631/677/685/687/689/690 Pin Diagram (QFN) RA3/MCLR/VPP 1 (1) 2 RC5/CCP1/P1A RA4/AN3/T1G/OSC2/CLKOUT RA5/T1CKI/OSC1/CLKIN VDD VSS RA0/AN0/C1IN+/ICSPDAT/ULPWU 20 19 18 17 16 20-pin QFN PIC16F631/677/ 685/687/689/690 15 RA1/AN1/C12IN0-/VREF/ICSPCLK 14 RA2/AN2/T0CKI/INT/C1OUT 13 RC0/AN4/C2IN+ 11 RC2/AN6/C12IN2-/P1D(1) RB4/AN10/SDI/SDA(2) RB7/TX/CK (3) 6 RC7/AN9/SDO(2) Note 1: 9 5 RC6/AN8/SS 10 RC1/AN5/C12IN1- RB5/AN11/RX/DT(3) 12 7 4 (2)
PAGE 10
PIC16F631/677/685/687/689/690 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 Memory Organization ................................................................................................................................................................. 25 3.0 Oscillator Module (With Fail-Safe Clock Monitor)..............................
PAGE 11
PIC16F631/677/685/687/689/690 1.0 DEVICE OVERVIEW Block Diagrams and pinout descriptions of the devices are as follows: The PIC16F631/677/685/687/689/690 devices are covered by this data sheet. They are available in 20-pin PDIP, SOIC, TSSOP and QFN packages.
PAGE 12
PIC16F631/677/685/687/689/690 FIGURE 1-2: PIC16F677 BLOCK DIAGRAM INT Configuration 13 8 Data Bus Program Counter PORTA Flash RA0 RA1 RA2 RA3 RA4 RA5 2K x 14 Program RAM 128 bytes File Registers 8-Level Stack (13-bit) Memory Program 14 Bus 9 RAM Addr PORTB Addr MUX Instruction Reg 7 Direct Addr 8 Indirect Addr RB4 RB5 RB6 RB7 FSR Reg STATUS Reg 8 PORTC 3 Instruction Decode and Control Power-up Timer Oscillator Start-up Timer OSC1/CLKI OSC2/CLKO ALU Power-on Reset Timing Generatio
PAGE 13
PIC16F631/677/685/687/689/690 FIGURE 1-3: PIC16F685 BLOCK DIAGRAM INT Configuration 13 8 Data Bus Program Counter PORTA Flash RA0 RA1 RA2 RA3 RA4 RA5 4K x 14 Program RAM 256 bytes File Registers 8-Level Stack (13-bit) Memory Program 14 Bus 9 RAM Addr PORTB Addr MUX Instruction Reg 7 Direct Addr 8 Indirect Addr RB4 RB5 RB6 RB7 FSR Reg STATUS Reg 8 PORTC 3 Instruction Decode and Control Power-up Timer Oscillator Start-up Timer OSC1/CLKI OSC2/CLKO ALU Power-on Reset Timing Generation
PAGE 14
PIC16F631/677/685/687/689/690 FIGURE 1-4: PIC16F687/PIC16F689 BLOCK DIAGRAM INT Configuration 13 8 Data Bus Program Counter PORTA Flash RA0 RA1 RA2 RA3 RA4 RA5 2K(1)/4K x 14 Program RAM 128(1)/256 bytes File Registers 8-Level Stack (13-bit) Memory Program 14 Bus 9 RAM Addr PORTB Addr MUX Instruction Reg 7 Direct Addr Indirect Addr 8 RB4 RB5 RB6 RB7 FSR Reg STATUS Reg 8 PORTC 3 Power-up Timer Instruction Decode and Control Oscillator Start-up Timer OSC1/CLKI OSC2/CLKO ALU Power-on
PAGE 15
PIC16F631/677/685/687/689/690 FIGURE 1-5: PIC16F690 BLOCK DIAGRAM INT Configuration 13 8 Data Bus Program Counter PORTA Flash RA0 RA1 RA2 RA3 RA4 RA5 4k x 14 Program RAM 256 bytes File Registers 8-Level Stack (13-bit) Memory Program 14 Bus 9 RAM Addr PORTB Addr MUX Instruction Reg Direct Addr 7 8 Indirect Addr RB4 RB5 RB6 RB7 FSR Reg STATUS Reg 8 PORTC 3 Power-up Timer Instruction Decode and Control Oscillator Start-up Timer OSC1/CLKI OSC2/CLKO Power-on Reset Timing Generation RC
PAGE 16
PIC16F631/677/685/687/689/690 TABLE 1-1: PINOUT DESCRIPTION – PIC16F631 Name RA0/C1IN+/ICSPDAT/ULPWU RA1/C12IN0-/ICSPCLK RA2/T0CKI/INT/C1OUT RA3/MCLR/VPP RA4/T1G/OSC2/CLKOUT RA5/T1CKI/OSC1/CLKIN Function Input Type RA0 TTL C1IN+ AN ICSPDAT ST ULPWU AN RA1 TTL Output Type Description CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. — Comparator C1 non-inverting input. CMOS ICSP™ Data I/O. — Ultra Low-Power Wake-up input.
PAGE 17
PIC16F631/677/685/687/689/690 TABLE 1-1: PINOUT DESCRIPTION – PIC16F631 (CONTINUED) Function Input Type RC6 RC6 ST CMOS General purpose I/O. RC7 RC7 ST CMOS General purpose I/O. VSS VSS Power — Ground reference. VDD VDD Power — Positive supply. Name Legend: AN = Analog input or output TTL = TTL compatible input HV = High Voltage © 2008 Microchip Technology Inc.
PAGE 18
PIC16F631/677/685/687/689/690 TABLE 1-2: PINOUT DESCRIPTION – PIC16F677 Name RA0/AN0/C1IN+/ICSPDAT/ ULPWU RA1/AN1/C12IN0-/VREF/ ICSPCLK RA2/AN2/T0CKI/INT/C1OUT RA3/MCLR/VPP RA4/AN3/T1G/OSC2/CLKOUT RA5/T1CKI/OSC1/CLKIN RB4/AN10/SDI/SDA RB5/AN11 RB6/SCK/SCL Legend: Function Input Type RA0 TTL Description CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. AN0 AN — A/D Channel 0 input. C1IN+ AN — Comparator C1 non-inverting input.
PAGE 19
PIC16F631/677/685/687/689/690 TABLE 1-2: PINOUT DESCRIPTION – PIC16F677 (CONTINUED) Function Input Type RB7 RB7 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. RC0/AN4/C2IN+ RC0 ST CMOS General purpose I/O. AN4 AN C2IN+ AN RC1 ST Name RC1/AN5/C12IN1- RC2/AN6/C12IN2- RC3/AN7/C12IN3- RC4/C2OUT Output Type Description — A/D Channel 4 input. — Comparator C2 non-inverting input. CMOS General purpose I/O.
PAGE 20
PIC16F631/677/685/687/689/690 TABLE 1-3: PINOUT DESCRIPTION – PIC16F685 Name RA0/AN0/C1IN+/ICSPDAT/ ULPWU RA1/AN1/C12IN0-/VREF/ICSPCLK RA2/AN2/T0CKI/INT/C1OUT RA3/MCLR/VPP RA4/AN3/T1G/OSC2/CLKOUT RA5/T1CKI/OSC1/CLKIN RB4/AN10 RB5/AN11 Function Input Type RA0 TTL Output Type Description CMOS General purpose I/O. Individually controlled interrupt-onchange. Individually enabled pull-up. AN0 AN — A/D Channel 0 input. C1IN+ AN — Comparator C1 positive input.
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PIC16F631/677/685/687/689/690 TABLE 1-3: PINOUT DESCRIPTION – PIC16F685 (CONTINUED) Name RC1/AN5/C12IN1- RC2/AN6/C12IN2-/P1D RC3/AN7/C12IN3-/P1C RC4/C2OUT/P1B RC5/CCP1/P1A Function Input Type RC1 ST Output Type Description CMOS General purpose I/O. AN5 AN — A/D Channel 5 input. C12IN1- AN — Comparator C1 or C2 negative input. RC2 ST AN6 AN CMOS General purpose I/O. C12IN2- AN P1D — CMOS PWM output. RC3 ST CMOS General purpose I/O.
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PIC16F631/677/685/687/689/690 TABLE 1-4: PINOUT DESCRIPTION – PIC16F687/PIC16F689 Name RA0/AN0/C1IN+/ICSPDAT/ ULPWU RA1/AN1/C12IN0-/VREF/ICSPCLK RA2/AN2/T0CKI/INT/C1OUT RA3/MCLR/VPP RA4/AN3/T1G/OSC2/CLKOUT RA5/T1CKI/OSC1/CLKIN RB4/AN10/SDI/SDA RB5/AN11/RX/DT Function Input Type RA0 TTL CMOS General purpose I/O. Individually controlled interrupt-onchange. Individually enabled pull-up. AN0 AN — A/D Channel 0 input. AN — Comparator C1 positive input.
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PIC16F631/677/685/687/689/690 TABLE 1-4: PINOUT DESCRIPTION – PIC16F687/PIC16F689 (CONTINUED) Name RB6/SCK/SCL RB7/TX/CK RC0/AN4/C2IN+ RC1/AN5/C12IN1- RC2/AN6/C12IN2- RC3/AN7/C12IN3- RC4/C2OUT Function Input Type Output Type RB6 TTL CMOS General purpose I/O. Individually controlled interrupt-onchange. Individually enabled pull-up. SCK ST CMOS SPI clock. SCL ST RB7 TTL TX — OD Description I2C™ clock. CMOS General purpose I/O. Individually controlled interrupt-onchange.
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PIC16F631/677/685/687/689/690 TABLE 1-5: PINOUT DESCRIPTION – PIC16F690 Name RA0/AN0/C1IN+/ICSPDAT/ ULPWU RA1/AN1/C12IN0-/VREF/ICSPCLK RA2/AN2/T0CKI/INT/C1OUT RA3/MCLR/VPP RA4/AN3/T1G/OSC2/CLKOUT RA5/T1CKI/OSC1/CLKIN RB4/AN10/SDI/SDA RB5/AN11/RX/DT Function Input Type RA0 TTL CMOS General purpose I/O. Individually controlled interrupt-onchange. Individually enabled pull-up. AN0 AN — A/D Channel 0 input. AN — Comparator C1 positive input.
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PIC16F631/677/685/687/689/690 TABLE 1-5: PINOUT DESCRIPTION – PIC16F690 (CONTINUED) Name RB6/SCK/SCL RB7/TX/CK RC0/AN4/C2IN+ RC1/AN5/C12IN1- RC2/AN6/C12IN2-/P1D RC3/AN7/C12IN3-/P1C RC4/C2OUT/P1B RC5/CCP1/P1A RC6/AN8/SS RC7/AN9/SDO VSS Input Type RB6 TTL CMOS General purpose I/O. Individually controlled interrupt-onchange. Individually enabled pull-up. SCK ST CMOS SPI clock. SCL ST RB7 TTL TX — OD Description I2C™ clock. CMOS General purpose I/O.
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PIC16F631/677/685/687/689/690 2.0 MEMORY ORGANIZATION 2.1 Program Memory Organization The PIC16F631/677/685/687/689/690 has a 13-bit program counter capable of addressing an 8K x 14 program memory space. Only the first 1K x 14 (0000h-03FFh) is physically implemented for the PIC16F631, the first 2K x 14 (0000h-07FFh) for the PIC16F677/PIC16F687, and the first 4K x 14 (0000h-0FFFh) for the PIC16F685/PIC16F689/ PIC16F690. Accessing a location above these boundaries will cause a wraparound.
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PIC16F631/677/685/687/689/690 2.2 Data Memory Organization The data memory (see Figures 2-6 through 2-8) is partitioned into four banks which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). The Special Function Registers are located in the first 32 locations of each bank. The General Purpose Registers, implemented as static RAM, are located in the last 96 locations of each Bank.
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PIC16F631/677/685/687/689/690 FIGURE 2-4: PIC16F631 SPECIAL FUNCTION REGISTERS File Address Indirect addr. (1) TMR0 PCL STATUS FSR PORTA PORTB PORTC PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON General Purpose Registers 64 Bytes 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch Indirect addr.
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PIC16F631/677/685/687/689/690 FIGURE 2-5: PIC16F677 SPECIAL FUNCTION REGISTERS File Address Indirect addr. (1) TMR0 PCL STATUS FSR PORTA PORTB PORTC PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON SSPBUF SSPCON ADRESH ADCON0 File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch Indirect addr.
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PIC16F631/677/685/687/689/690 FIGURE 2-6: PIC16F685 SPECIAL FUNCTION REGISTERS File Address Indirect addr. (1) TMR0 PCL STATUS FSR PORTA PORTB PORTC PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON CCPR1L CCPR1H CCP1CON PWM1CON ECCPAS ADRESH ADCON0 File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch Indirect addr.
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PIC16F631/677/685/687/689/690 FIGURE 2-7: PIC16F687/PIC16F689 SPECIAL FUNCTION REGISTERS File Address Indirect addr. (1) TMR0 PCL STATUS FSR PORTA PORTB PORTC File Address Indirect addr. (1) OPTION_REG PCL STATUS FSR TRISA TRISB TRISC PCLATH INTCON PIR1 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch PIR2 0Dh TMR1L 0Eh Indirect addr. (1) TMR0 PCL STATUS FSR PORTA PORTB PORTC PCLATH INTCON PIE1 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch PIE2 PCON Indirect addr.
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PIC16F631/677/685/687/689/690 FIGURE 2-8: PIC16F690 SPECIAL FUNCTION REGISTERS File Address Indirect addr. (1) TMR0 PCL STATUS FSR PORTA PORTB PORTC File Address Indirect addr.
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PIC16F631/677/685/687/689/690 TABLE 2-1: Addr PIC16F631/677/685/687/689/690 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 44,205 01h TMR0 Timer0 Module Register xxxx xxxx 81,205 02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 44,205 03h STATUS 0001 1xxx 36,205 IRP RP1
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PIC16F631/677/685/687/689/690 TABLE 2-2: Addr PIC16F631/677/685/687/689/690 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page xxxx xxxx 44,205 Bank 1 80h INDF 81h OPTION_REG Addressing this location uses contents of FSR to address data memory (not a physical register) 82h PCL RABPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Program Counter’s (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C 83h STATUS 84h F
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PIC16F631/677/685/687/689/690 TABLE 2-3: Addr Name PIC16F631/677/685/687/689/690 SPECIAL FUNCTION REGISTERS SUMMARY BANK 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page Bank 2 100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 44,205 101h TMR0 Timer0 Module Register xxxx xxxx 81,205 102h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 44,205 103h STATUS 0001 1xxx 36,205 104h F
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PIC16F631/677/685/687/689/690 TABLE 2-4: Addr PIC16F631/677/685/687/689/690 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page Bank 3 180h INDF 181h OPTION_REG Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 182h PCL 183h STATUS RABPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Program Counter’s (PC) Least Significant Byte IRP RP1 1111 1111 44,205 37,205 0000 000
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PIC16F631/677/685/687/689/690 2.2.2.1 STATUS Register The STATUS register, shown in Register 2-1, contains: • the arithmetic status of the ALU • the Reset status • the bank select bits for data memory (GPR and SFR) The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic.
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PIC16F631/677/685/687/689/690 2.2.2.2 OPTION Register Note: The OPTION register, shown in Register 2-2, is a readable and writable register, which contains various control bits to configure: • • • • Timer0/WDT prescaler External RA2/INT interrupt Timer0 Weak pull-ups on PORTA/PORTB REGISTER 2-2: To achieve a 1:1 prescaler assignment for Timer0, assign the prescaler to the WDT by setting PSA bit of the OPTION register to ‘1’. See Section 6.3 “Timer1 Prescaler”.
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PIC16F631/677/685/687/689/690 2.2.2.3 INTCON Register Note: The INTCON register, shown in Register 2-3, is a readable and writable register, which contains the various enable and flag bits for TMR0 register overflow, PORTA change and external RA2/AN2/T0CKI/INT/C1OUT pin interrupts. REGISTER 2-3: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE of the INTCON register.
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PIC16F631/677/685/687/689/690 2.2.2.4 PIE1 Register The PIE1 register contains the interrupt enable bits, as shown in Register 2-4. REGISTER 2-4: Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.
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PIC16F631/677/685/687/689/690 2.2.2.5 PIE2 Register The PIE2 register contains the interrupt enable bits, as shown in Register 2-5. REGISTER 2-5: Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.
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PIC16F631/677/685/687/689/690 2.2.2.6 PIR1 Register The PIR1 register contains the interrupt flag bits, as shown in Register 2-6. REGISTER 2-6: Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
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PIC16F631/677/685/687/689/690 2.2.2.7 PIR2 Register The PIR2 register contains the interrupt flag bits, as shown in Register 2-7. REGISTER 2-7: Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
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PIC16F631/677/685/687/689/690 2.2.2.8 PCON Register The Power Control (PCON) register (see Register 2-8) contains flag bits to differentiate between a: • • • • Power-on Reset (POR) Brown-out Reset (BOR) Watchdog Timer Reset (WDT) External MCLR Reset The PCON register also controls the Ultra Low-Power Wake-up and software enable of the BOR.
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PIC16F631/677/685/687/689/690 2.3 PCL and PCLATH 2.3.2 The Program Counter (PC) is 13 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 2-9 shows the two situations for the loading of the PC. The upper example in Figure 2-9 shows how the PC is loaded on a write to PCL (PCLATH<4:0> → PCH).
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PIC16F631/677/685/687/689/690 FIGURE 2-10: DIRECT/INDIRECT ADDRESSING PIC16F631/677/685/687/689/690 Direct Addressing RP1 RP0 Bank Select 6 From Opcode Indirect Addressing 0 IRP 7 Bank Select Location Select 00 01 10 File Select Register 0 Location Select 11 00h 180h Data Memory 7Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 For memory map detail, see Figures 2-6, 2-7 and 2-8. © 2008 Microchip Technology Inc.
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PIC16F631/677/685/687/689/690 3.0 OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR) 3.1 Overview The Oscillator module can be configured in one of eight clock modes. 1. 2. 3. The Oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 3-1 illustrates a block diagram of the Oscillator module. 4. 5.
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PIC16F631/677/685/687/689/690 3.2 Oscillator Control The Oscillator Control (OSCCON) register (Figure 3-1) controls the system clock and frequency selection options.
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PIC16F631/677/685/687/689/690 3.3 Clock Source Modes Clock Source modes can be classified as external or internal. • External Clock modes rely on external circuitry for the clock source. Examples are: Oscillator modules (EC mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and Resistor-Capacitor (RC) mode circuits. • Internal clock sources are contained internally within the Oscillator module.
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PIC16F631/677/685/687/689/690 3.4.3 LP, XT, HS MODES The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure 3-3). The mode selects a low, medium or high gain setting of the internal inverteramplifier to support various resonator types and speed. LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current consumption is the least of the three modes. This mode is designed to drive only 32.
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PIC16F631/677/685/687/689/690 3.4.4 3.5 EXTERNAL RC MODES The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. There are two modes: RC and RCIO. In RC mode, the RC circuit connects to OSC1. OSC2/ CLKOUT outputs the RC oscillator frequency divided by 4.
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PIC16F631/677/685/687/689/690 3.5.2.1 OSCTUNE Register The HFINTOSC is factory calibrated but can be adjusted in software by writing to the OSCTUNE register (Register 3-2). The default value of the OSCTUNE register is ‘0’. The value is a 5-bit two’s complement number. REGISTER 3-2: When the OSCTUNE register is modified, the HFINTOSC frequency will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred.
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PIC16F631/677/685/687/689/690 3.5.3 LFINTOSC The Low-Frequency Internal Oscillator (LFINTOSC) is an uncalibrated 31 kHz internal clock source. The output of the LFINTOSC connects to a postscaler and multiplexer (see Figure 3-1). Select 31 kHz, via software, using the IRCF<2:0> bits of the OSCCON register. See Section 3.5.4 “Frequency Select Bits (IRCF)” for more information. The LFINTOSC is also the frequency for the Power-up Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM).
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PIC16F631/677/685/687/689/690 FIGURE 3-6: HFINTOSC INTERNAL OSCILLATOR SWITCH TIMING LFINTOSC (FSCM and WDT disabled) HFINTOSC Start-up Time 2-cycle Sync Running LFINTOSC IRCF <2:0> ≠0 =0 System Clock HFINTOSC LFINTOSC (Either FSCM or WDT enabled) HFINTOSC 2-cycle Sync Running LFINTOSC ≠0 IRCF <2:0> =0 System Clock LFINTOSC HFINTOSC LFINTOSC turns off unless WDT or FSCM is enabled LFINTOSC Start-up Time 2-cycle Sync Running HFINTOSC IRCF <2:0> =0 ¼0 System Clock DS41262E-page 5
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PIC16F631/677/685/687/689/690 3.6 Clock Switching The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bit of the OSCCON register. 3.6.1 SYSTEM CLOCK SELECT (SCS) BIT The System Clock Select (SCS) bit of the OSCCON register selects the system clock source that is used for the CPU and peripherals.
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PIC16F631/677/685/687/689/690 3.7.3 CHECKING TWO-SPEED CLOCK STATUS Checking the state of the OSTS bit of the OSCCON register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Word register (CONFIG), or the internal oscillator. FIGURE 3-7: TWO-SPEED START-UP HFINTOSC TOST OSC1 0 1 1022 1023 OSC2 Program Counter PC - N PC PC + 1 System Clock DS41262E-page 56 © 2008 Microchip Technology Inc.
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PIC16F631/677/685/687/689/690 3.8 Fail-Safe Clock Monitor 3.8.3 The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator fail. The FSCM can detect oscillator failure any time after the Oscillator Start-up Timer (OST) has expired. The FSCM is enabled by setting the FCMEN bit in the Configuration Word register (CONFIG). The FSCM is applicable to all external Oscillator modes (LP, XT, HS, EC, RC and RCIO).
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PIC16F631/677/685/687/689/690 FIGURE 3-9: FSCM TIMING DIAGRAM Sample Clock Oscillator Failure System Clock Output Clock Monitor Output (Q) Failure Detected OSCFIF Test Note: Test The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity.
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PIC16F631/677/685/687/689/690 4.0 I/O PORTS port pins are read, this value is modified and then written to the PORT data latch. RA3 reads ‘0’ when MCLRE = 1. There are as many as eighteen general purpose I/O pins available. Depending on which peripherals are enabled, some or all of the pins may not be available as general purpose I/O. In general, when a peripheral is enabled, the associated pin may not be used as a general purpose I/O pin. 4.
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PIC16F631/677/685/687/689/690 4.2 Additional Pin Functions 4.2.3 INTERRUPT-ON-CHANGE Every PORTA pin on this device family has an interrupt-on-change option and a weak pull-up option. RA0 also has an Ultra Low-Power Wake-up option. The next three sections describe these functions. Each PORTA pin is individually configurable as an interrupt-on-change pin. Control bits IOCAx enable or disable the interrupt function for each pin. Refer to Register 4-6.
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PIC16F631/677/685/687/689/690 REGISTER 4-3: ANSEL: ANALOG SELECT REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown ANS<7:0>: Analog Select bits Analog select between analog or digital function on pins AN<7:0>, respectively. 1 = Analog input.
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PIC16F631/677/685/687/689/690 REGISTER 4-5: WPUA: PORTA REGISTER U-0 U-0 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1 — — WPUA5 WPUA4 — WPUA2 WPUA1 WPUA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 WPUA<5:4>: Weak Pull-up Register bit 1 = Pull-up enabled 0 = Pull-up disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 WPUA<2:0>: Weak Pull-up Regis
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PIC16F631/677/685/687/689/690 4.2.4 ULTRA LOW-POWER WAKE-UP The Ultra Low-Power Wake-up (ULPWU) on RA0 allows a slow falling voltage to generate an interrupt-on-change on RA0 without excess current consumption. The mode is selected by setting the ULPWUE bit of the PCON register. This enables a small current sink, which can be used to discharge a capacitor on RA0. Follow these steps to use this feature: a) b) c) d) e) Charge the capacitor on RA0 by configuring the RA0 pin to output (= 1).
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PIC16F631/677/685/687/689/690 4.2.5 PIN DESCRIPTIONS AND DIAGRAMS 4.2.5.1 Figure 4-2 shows the diagram for this pin. The RA0/AN0/C1IN+/ICSPDAT/ULPWU pin is configurable to function as one of the following: Each PORTA pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the comparator or the A/D Converter (ADC), refer to the appropriate section in this data sheet.
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PIC16F631/677/685/687/689/690 4.2.5.2 RA1/AN1/C12IN0-/VREF/ICSPCLK 4.2.5.3 RA2/AN2/T0CKI/INT/C1OUT Figure 4-2 shows the diagram for this pin. The RA1/AN1/C12IN0-/VREF/ICSPCLK pin is configurable to function as one of the following: Figure 4-3 shows the diagram for this pin.
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PIC16F631/677/685/687/689/690 4.2.5.4 4.2.5.5 RA3/MCLR/VPP RA4/AN3/T1G/OSC2/CLKOUT Figure 4-4 shows the diagram for this pin. The RA3/MCLR/VPP pin is configurable to function as one of the following: Figure 4-5 shows the diagram for this pin.
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PIC16F631/677/685/687/689/690 4.2.5.6 RA5/T1CKI/OSC1/CLKIN Figure 4-6 shows the diagram for this pin.
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PIC16F631/677/685/687/689/690 TABLE 4-1: Name ADCON0 SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets ADFM VCFG CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000 0000 0000 ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111 CM1CON0 C1ON C1OUT C1OE C1POL — C1R C1CH1 C1CH0 0000 -000 0000 -000 GIE PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 000x 0000 000x — — IOCA5
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PIC16F631/677/685/687/689/690 4.3 PORTB and TRISB Registers 4.4.1 PORTB is a 4-bit wide, bidirectional port. The corresponding data direction register is TRISB (Register 4-6). Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin).
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PIC16F631/677/685/687/689/690 REGISTER 4-8: TRISB: PORTB TRI-STATE REGISTER R/W-1 R/W-1 R/W-1 R/W-1 U-0 U-0 U-0 U-0 TRISB7 TRISB6 TRISB5 TRISB4 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 TRISB<7:4>: PORTB Tri-State Control bit 1 = PORTB pin configured as an input (tri-stated) 0 = PORTB pin configured as an output bit 3-0 Unimplemented: Read as ‘0’ REGISTER 4-9:
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PIC16F631/677/685/687/689/690 4.4.3 PIN DESCRIPTIONS AND DIAGRAMS Each PORTB pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the SSP, I2C™ or interrupts, refer to the appropriate section in this data sheet. 4.4.3.1 RB4/AN10/SDI/SDA Figure 4-7 shows the diagram for this pin.
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PIC16F631/677/685/687/689/690 4.4.3.2 RB5/AN11/RX/DT(1, 2) Figure 4-8 shows the diagram for this pin. The RB5/AN11/RX/DT pin is configurable to function as one of the following: • • • • a general purpose I/O an analog input for the ADC (except PIC16F631) an asynchronous serial input a synchronous serial data I/O FIGURE 4-8: Data Bus D WR WPUB Q Analog(1) Input Mode VDD CK Q Weak RABPU RD WPUB SYNC SPEN Note 1: RX and DT are available on PIC16F687/PIC16F689/PIC16F690 only.
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PIC16F631/677/685/687/689/690 4.4.3.3 RB6/SCK/SCL FIGURE 4-9: Figure 4-9 shows the diagram for this pin. The RB6/SCK/SCL(1) pin is configurable to function as one of the following: • a general purpose I/O • a SPI clock • an I2C™ clock Note 1: SCK and SCL are available PIC16F677/PIC16F687/PIC16F689/ PIC16F690 only.
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PIC16F631/677/685/687/689/690 4.4.3.4 RB7/TX/CK Figure 4-10 shows the diagram for this pin. The RB7/TX/CK(1) pin is configurable to function as one of the following: • a general purpose I/O • an asynchronous serial output • a synchronous clock I/O FIGURE 4-10: Data Bus WR WPUB D BLOCK DIAGRAM OF RB7 Q VDD CK Q Weak RABPU RD WPUB SPEN Note 1: TX and CK are available on PIC16F687/PIC16F689/PIC16F690 only.
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PIC16F631/677/685/687/689/690 TABLE 4-2: Name IOCB INTCON PORTB SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bit 7 Bit 6 Bit 5 Bit 4 IOCB7 IOCB6 IOCB5 IOCB4 — — — — 0000 ---- 0000 ---- GIE PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 000x 0000 000x RB7 RB6 RB5 RB4 — — — — xxxx ---- uuuu ---- TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 1111 ---- 1111 ---- WPUB WPUB7 WPUB6 WPUB5 WPUB4 — — — — 1111 -
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PIC16F631/677/685/687/689/690 4.5 PORTC and TRISC Registers The TRISC register controls the PORTC pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISC register are maintained set when using them as analog inputs. I/O pins configured as analog input always read ‘0’. PORTC is a 8-bit wide, bidirectional port. The corresponding data direction register is TRISC (Register 4-10).
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PIC16F631/677/685/687/689/690 4.5.1 RC0/AN4/C2IN+ 4.5.3 RC2/AN6/C12IN2-/P1D The RC0 is configurable to function as one of the following: The RC2/AN6/P1D(1) is configurable to function as one of the following: • a general purpose I/O • an analog input for the ADC (except PIC16F631) • an analog input to Comparator C2 • • • • 4.5.
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PIC16F631/677/685/687/689/690 4.5.5 RC4/C2OUT/P1B (1, 2) The RC4/C2OUT/P1B as one of the following: 4.5.6 is configurable to function • a general purpose I/O • a digital output from Comparator C2 • a PWM output RC5/CCP1/P1A The RC5/CCP1/P1A(1) is configurable to function as one of the following: • a general purpose I/O • a digital input/output for the Enhanced CCP • a PWM output Note 1: Enabling both C2OUT and P1B will cause a conflict on RC4 and create unpredictable results.
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PIC16F631/677/685/687/689/690 4.5.7 RC6/AN8/SS The RC6/AN8/SS of the following: (1,2) 4.5.8 is configurable to function as one • a general purpose I/O • an analog input for the ADC (except PIC16F631) • a slave select input Note 1: SS is available on PIC16F687/PIC16F689/PIC16F690 only.
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PIC16F631/677/685/687/689/690 TABLE 4-3: Name ANSEL ANSELH SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bit 7 Bit 6 Bit 5 Bit 4 ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111 — — — — ANS11 ANS10 ANS9 ANS8 ---- 1111 ---- 1111 CCP1CON(2) P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000 CM2CON0 C2ON C2OUT C2OE C2POL — C2R C2CH1 C2CH0 0000 -000 0000 -000 CM2CON
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PIC16F631/677/685/687/689/690 5.0 TIMER0 MODULE 5.1 Timer0 Operation The Timer0 module is an 8-bit timer/counter with the following features: When used as a timer, the Timer0 module can be used as either an 8-bit timer or an 8-bit counter. • • • • • 5.1.
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PIC16F631/677/685/687/689/690 5.1.3 SOFTWARE PROGRAMMABLE PRESCALER A single software programmable prescaler is available for use with either Timer0 or the Watchdog Timer (WDT), but not both simultaneously. The prescaler assignment is controlled by the PSA bit of the OPTION register. To assign the prescaler to Timer0, the PSA bit must be cleared to a ‘0’. There are 8 prescaler options for the Timer0 module ranging from 1:2 to 1:256.
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PIC16F631/677/685/687/689/690 REGISTER 5-1: OPTION_REG: OPTION REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RABPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RABPU: PORTA/PORTB Pull-up Enable bit 1 = Pull-ups on PORTA/PORTB are disabled 0 = Pull-ups on PORTA/PORTB are disabled by individual WPUAx control bits b
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PIC16F631/677/685/687/689/690 6.0 TIMER1 MODULE WITH GATE CONTROL 6.1 The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter.
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PIC16F631/677/685/687/689/690 6.2.1 INTERNAL CLOCK SOURCE When the internal clock source is selected the TMR1H:TMR1L register pair will increment on multiples of FOSC as determined by the Timer1 prescaler. 6.2.2 TRISA5 and TRISA4 bits are set when the Timer1 oscillator is enabled. RA5 and RA4 bits read as ‘0’ and TRISA5 and TRISA4 bits read as ‘1’. Note: EXTERNAL CLOCK SOURCE When the external clock source is selected, the Timer1 module may work as a timer or a counter.
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PIC16F631/677/685/687/689/690 Note: TMR1GE bit of the T1CON register must be set to use either T1G or C2OUT as the Timer1 gate source. See the CM2CON1 register (Register 8-3) for more information on selecting the Timer1 gate source. Timer1 gate can be inverted using the T1GINV bit of the T1CON register, whether it originates from the T1G pin or Comparator C2 output. This configures Timer1 to measure either the active-high or active-low time between events. 6.
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PIC16F631/677/685/687/689/690 FIGURE 6-2: TIMER1 INCREMENTING EDGE T1CKI = 1 when TMR1 Enabled T1CKI = 0 when TMR1 Enabled Note 1: 2: Arrows indicate counter increments. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. © 2008 Microchip Technology Inc.
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PIC16F631/677/685/687/689/690 6.12 Timer1 Control Register The Timer1 Control register (T1CON), shown in Register 6-1, is used to control Timer1 and select the various features of the Timer1 module.
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PIC16F631/677/685/687/689/690 TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Name Bit 7 Bit 6 CM2CON1 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets MC1OUT MC2OUT — — — — T1GSS C2SYNC ---- --10 ---- --10 INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 0000 0000 0000 PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000 PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000 uuuu
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PIC16F631/677/685/687/689/690 7.0 TIMER2 MODULE The Timer2 module is an eight-bit timer with the following features: • • • • • 8-bit timer register (TMR2) 8-bit period register (PR2) Interrupt on TMR2 match with PR2 Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) Timer2 is turned on by setting the TMR2ON bit in the T2CON register to a ‘1’. Timer2 is turned off by clearing the TMR2ON bit to a ‘0’.
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PIC16F631/677/685/687/689/690 T2CON: TIMER 2 CONTROL REGISTER(1) REGISTER 7-1: U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS<3:0>: Timer2 Output Postscaler Select bits 0000 = 1:1 Postscaler 0001 = 1:2 Postscaler 0010 = 1:3 Postscaler
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PIC16F631/677/685/687/689/690 8.0 COMPARATOR MODULE Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. The comparators are very useful mixed signal building blocks because they provide analog functionality independent of program execution.
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PIC16F631/677/685/687/689/690 FIGURE 8-2: COMPARATOR C1 SIMPLIFIED BLOCK DIAGRAM C1CH<1:0> C1POL 2 D Q1 C12IN0- 0 C12IN1C12IN2- 1 MUX 2 C12IN3- 3 Q EN To Data Bus RD_CM1CON0 D Q Set C1IF Q3*RD_CM1CON0 EN CL NRESET C1ON(1) To other peripherals C1R C1IN+ FixedRef CVREF 0 MUX 1 0 MUX 1 C1OUT (to SR latch) C1OUT C1POL Note 1: 2: 3: C1VREN FIGURE 8-3: C1VIN- C1VIN+ C1 + When C1ON = 0, the C1 comparator will produce a ‘0’ output to the XOR Gate.
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PIC16F631/677/685/687/689/690 8.2 Comparator Control 8.2.4 COMPARATOR OUTPUT SELECTION Each comparator has a separate control and Configuration register: CM1CON0 for Comparator C1 and CM2CON0 for Comparator C2. In addition, Comparator C2 has a second control register, CM2CON1, for controlling the interaction with Timer1 and simultaneous reading of both comparator outputs.
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PIC16F631/677/685/687/689/690 8.4 Comparator Interrupt Operation The comparator interrupt flag can be set whenever there is a change in the output value of the comparator. Changes are recognized by means of a mismatch circuit which consists of two latches and an exclusiveor gate (see Figure 8-2 and Figure 8-3). One latch is updated with the comparator output level when the CMxCON0 register is read. This latch retains the value until the next read of the CMxCON0 register or the occurrence of a Reset.
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PIC16F631/677/685/687/689/690 8.5 Operation During Sleep The comparator, if enabled before entering Sleep mode, remains active during Sleep. The additional current consumed by the comparator is shown separately in the Section 17.0 “Electrical Specifications”. If the comparator is not used to wake the device, power consumption can be minimized while in Sleep mode by turning off the comparator. Each comparator is turned off by clearing the CxON bit of the CMxCON0 register.
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PIC16F631/677/685/687/689/690 REGISTER 8-1: CM1CON0: COMPARATOR C1 CONTROL REGISTER 0 R/W-0 R-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 C1ON C1OUT C1OE C1POL — C1R C1CH1 C1CH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 C1ON: Comparator C1 Enable bit 1 = Comparator C1 is enabled 0 = Comparator C1 is disabled bit 6 C1OUT: Comparator C1 Output bit If C1POL = 1 (inverted polarity):
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PIC16F631/677/685/687/689/690 REGISTER 8-2: CM2CON0: COMPARATOR C2 CONTROL REGISTER 0 R/W-0 R-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 C2ON C2OUT C2OE C2POL — C2R C2CH1 C2CH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 C2ON: Comparator C2 Enable bit 1 = Comparator C2 is enabled 0 = Comparator C2 is disabled bit 6 C2OUT: Comparator C2 Output bit If C2POL = 1 (inverted polarity):
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PIC16F631/677/685/687/689/690 8.7 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 8-6. Since the analog input pins share their connection with a digital input, they have reverse biased ESD protection diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur.
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PIC16F631/677/685/687/689/690 8.8 Additional Comparator Features There are three additional comparator features: • Timer1 count enable (gate) • Synchronizing output with Timer1 • Simultaneous read of comparator outputs 8.8.1 COMPARATOR C2 GATING TIMER1 This feature can be used to time the duration or interval of analog events. Clearing the T1GSS bit of the CM2CON1 register will enable Timer1 to increment based on the output of Comparator C2. This requires that Timer1 is on and gating is enabled.
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PIC16F631/677/685/687/689/690 8.9 Comparator SR Latch 8.9.2 The SR<1:0> bits of the SRCON register control the latch output multiplexers and determine four possible output configurations. In these four configurations, the CxOUT I/O port logic is connected to: The SR Latch module provides additional control of the comparator outputs. The module consists of a single SR latch and output multiplexers. The SR latch can be set, reset or toggled by the comparator outputs.
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PIC16F631/677/685/687/689/690 REGISTER 8-4: SRCON: SR LATCH CONTROL REGISTER R/W-0 R/W-0 SR1(2) (2) SR0 R/W-0 R/W-0 R/S-0 R/S-0 U-0 U-0 C1SEN C2REN PULSS PULSR — — bit 7 bit 0 Legend: S = Bit is set only R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SR1: SR Latch Configuration bit(2) 1 = C2OUT pin is the latch Q output 0 = C2OUT pin is the C2 comparator output bit 6 SR0: S
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PIC16F631/677/685/687/689/690 8.10 Comparator Voltage Reference 8.10.3 OUTPUT CLAMPED TO VSS The comparator voltage reference module provides an internally generated voltage reference for the comparators. The following features are available: The CVREF output voltage can be set to Vss with no power consumption by clearing the VP6EN bit of the VRCON register. • • • • • This allows the comparator to detect a zero-crossing while not consuming additional CVREF module current.
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PIC16F631/677/685/687/689/690 8.10.5 FIXED VOLTAGE REFERENCE 8.10.7 The fixed voltage reference is independent of VDD, with a nominal output voltage of 0.6V. This reference can be enabled by setting the VP6EN bit of the VRCON register to ‘1’. This reference is always enabled when the HFINTOSC oscillator is active. 8.10.6 Multiplexers on the output of the Voltage Reference module enable selection of either the CVREF or fixed voltage reference for use by the comparators.
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PIC16F631/677/685/687/689/690 REGISTER 8-5: VRCON: VOLTAGE REFERENCE CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 C1VREN C2VREN VRR VP6EN VR3 VR2 VR1 VR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 C1VREN: Comparator 1 Voltage Reference Enable bit 1 = CVREF circuit powered on and routed to C1VREF input of Comparator C1 0 = 0.
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PIC16F631/677/685/687/689/690 9.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE Figure 9-1 shows the block diagram of the ADC. The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter.
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PIC16F631/677/685/687/689/690 9.1 ADC Configuration When configuring and using the ADC the following functions must be considered: • • • • • • Port configuration Channel selection ADC voltage reference selection ADC conversion clock source Interrupt control Results formatting 9.1.1 PORT CONFIGURATION The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin should be configured for analog by setting the associated TRIS and ANSEL bits.
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PIC16F631/677/685/687/689/690 TABLE 9-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES (VDD > 3.0V, VREF > 2.5V) ADC Clock Period (TAD) ADC Clock Source Device Frequency (FOSC) ADCS<2:0> 20 MHz 8 MHz (2) 2.0 μs 1.0 μs(2) 4.0 μs 2.0 μs 8.0 μs(3) 2.0 μs 4.0 μs 16.0 μs(3) 4.0 μs 8.0 μs(3) 32.0 μs(3) FOSC/2 000 100 ns 100 200 ns(2) 500 ns(2) 001 400 ns (2) (2) 800 ns (2) FOSC/16 101 FOSC/32 010 500 ns 1.0 μs (3) FOSC/64 110 3.
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PIC16F631/677/685/687/689/690 9.1.6 RESULT FORMATTING The 10-bit A/D conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON0 register controls the output format. Figure 9-3 shows the two output formats.
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PIC16F631/677/685/687/689/690 9.2 9.2.1 ADC Operation STARTING A CONVERSION To enable the ADC module, the ADON bit of the ADCON0 register must be set to a ‘1’. Setting the GO/ DONE bit of the ADCON0 register to a ‘1’ will start the Analog-to-Digital conversion. Note: 9.2.2 The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section 9.2.6 “A/D Conversion Procedure”.
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PIC16F631/677/685/687/689/690 EXAMPLE 9-1: A/D CONVERSION ;This code block configures the ADC ;for polling, Vdd reference, Frc clock ;and AN0 input. ; ;Conversion start & polling for completion ; are included.
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PIC16F631/677/685/687/689/690 REGISTER 9-1: ADCON0: A/D CONTROL REGISTER 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM VCFG CHS3 CHS2 CHS1 CHS0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ADFM: A/D Conversion Result Format Select bit 1 = Right justified 0 = Left justified bit 6 VCFG: Voltage Reference bit 1 = VREF pin 0 = VDD bit 5
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PIC16F631/677/685/687/689/690 REGISTER 9-2: ADCON1: A/D CONTROL REGISTER 1 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — ADCS2 ADCS1 ADCS0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 x11 = FRC (clock derived from a dedicated internal o
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PIC16F631/677/685/687/689/690 REGISTER 9-3: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x ADRES9 ADRES8 ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown ADRES<9:2>: ADC Result Register bits Upper 8 bits of 10-bit conversion result REGISTER 9-4: ADRESL: ADC RESULT
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PIC16F631/677/685/687/689/690 9.3 A/D Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 9-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure 9-4.
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PIC16F631/677/685/687/689/690 Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin leakage specification. FIGURE 9-4: ANALOG INPUT MODEL VDD Rs VA VT = 0.6V ANx CPIN 5 pF VT = 0.
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PIC16F631/677/685/687/689/690 TABLE 9-2: SUMMARY OF ASSOCIATED ADC REGISTERS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets ADCON0 ADFM VCFG CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000 0000 0000 ADCON1 ANSEL ANSELH — ADCS2 ADCS1 ADCS0 — — — — -000 ---- -000 ---- ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111 — — — — ANS11 ANS10 ANS9 ANS8 ---- 1111 ---- 1111 xxxx xxxx uuuu uuuu ADRESH A/D R
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PIC16F631/677/685/687/689/690 10.0 DATA EEPROM AND FLASH PROGRAM MEMORY CONTROL Data EEPROM memory is readable and writable and the Flash program memory (PIC16F685/PIC16F689/ PIC16F690 only) is readable during normal operation (full VDD range). These memories are not directly mapped in the register file space. Instead, they are indirectly addressed through the Special Function Registers (SFRs).
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PIC16F631/677/685/687/689/690 REGISTER 10-1: EEDAT: EEPROM DATA REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown EEDAT<7:0>: 8 Least Significant Address bits to Write to or Read from data EEPROM or Read from program memory REGISTER 10-2: EEADR: E
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PIC16F631/677/685/687/689/690 REGISTER 10-5: EECON1: EEPROM CONTROL REGISTER R/W-x U-0 U-0 U-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD(1) — — — WRERR WREN WR RD bit 7 bit 0 Legend: S = Bit can only be set R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EEPGD: Program/Data EEPROM Select bit(1) 1 = Accesses program memory 0 = Accesses data memory bit 6-4 Unimplemented: Read as ‘0’ bit 3
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PIC16F631/677/685/687/689/690 10.1.2 READING THE DATA EEPROM MEMORY 10.1.3 WRITING TO THE DATA EEPROM MEMORY To read a data memory location, the user must write the address to the EEADR register, clear the EEPGD control bit of the EECON1 register, and then set control bit RD. The data is available at the very next cycle, in the EEDAT register; therefore, it can be read in the next instruction. EEDAT will hold this value until another read or until it is written to by the user (during a write operation).
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PIC16F631/677/685/687/689/690 10.1.4 READING THE FLASH PROGRAM MEMORY (PIC16F685/PIC16F689/ PIC16F690) To read a program memory location, the user must write the Least and Most Significant address bits to the EEADR and EEADRH registers, set the EEPGD control bit of the EECON1 register, and then set control bit RD. Once the read control bit is set, the program memory Flash controller will use the second instruction cycle to read the data.
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PIC16F631/677/685/687/689/690 FIGURE 10-1: FLASH PROGRAM MEMORY READ CYCLE EXECUTION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC Flash ADDR Flash Data PC + 1 INSTR (PC) INSTR(PC - 1) executed here EEADRH,EEADR INSTR (PC + 1) BSF EECON1,RD executed here PC +3 PC+3 EEDATH,EEDAT INSTR(PC + 1) executed here PC + 5 PC + 4 INSTR (PC + 3) Forced NOP executed here INSTR (PC + 4) INSTR(PC + 3) executed here INSTR(PC + 4) executed here RD bit EEDATH EEDAT Register
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PIC16F631/677/685/687/689/690 10.2 Write Verify Depending on the application, good programming practice may dictate that the value written to the data EEPROM should be verified (see Example 10-4) to the desired value to be written. EXAMPLE 10-4: WRITE VERIFY BANKSEL EEDAT MOVF EEDAT, W BANKSEL EECON1 BSF EECON1, RD BANKSEL XORWF BTFSS GOTO : BANKSEL 10.2.1 When the data memory is code-protected, only the CPU is able to read and write data to the data EEPROM.
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PIC16F631/677/685/687/689/690 TABLE 10-1: SUMMARY OF REGISTERS ASSOCIATED WITH DATA EEPROM Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets EECON1 EEPGD(1) — — — WRERR WREN WR RD x--- x000 0--- q000 EECON2 EEPROM Control Register 2 (not a physical register) EEADR EEADR7(2) EEADR6 Name EEADRH(1) EEDAT EEDATH(1) INTCON PIE2 PIR2 Legend: Note 1: 2: EEADR5 ---- ---- ---- ---- EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000
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PIC16F631/677/685/687/689/690 11.0 ENHANCED CAPTURE/COMPARE/PWM MODULE Table 11-1 shows the timer resources required by the ECCP module. TABLE 11-1: The Enhanced Capture/Compare/PWM module is a peripheral which allows the user to time and control different events. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired.
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PIC16F631/677/685/687/689/690 11.1 Capture Mode 11.1.2 In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin CCP1. An event is defined as one of the following and is configured by the CCP1M<3:0> bits of the CCP1CON register: • • • • Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge When a capture is made, the Interrupt Request Flag bit CCP1IF of the PIR1 register is set. The interrupt flag must be cleared in software.
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PIC16F631/677/685/687/689/690 11.2 Compare Mode 11.2.2 In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the CCP module may: • • • • • Toggle the CCP1 output Set the CCP1 output Clear the CCP1 output Generate a Special Event Trigger Generate a Software Interrupt All Compare modes can generate an interrupt.
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PIC16F631/677/685/687/689/690 11.3 PWM Mode The PWM mode generates a Pulse-Width Modulated signal on the CCP1 pin. The duty cycle, period and resolution are determined by the following registers: • • • • PR2 T2CON CCPR1L CCP1CON FIGURE 11-4: CCP PWM OUTPUT Period Pulse Width In Pulse-Width Modulation (PWM) mode, the CCP module produces up to a 10-bit resolution PWM output on the CCP1 pin.
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PIC16F631/677/685/687/689/690 11.3.1 PWM PERIOD EQUATION 11-2: The PWM period is specified by the PR2 register of Timer2. The PWM period can be calculated using the formula of Equation 11-1. EQUATION 11-1: TOSC = 1/FOSC • TMR2 is cleared • The CCP1 pin is set. (Exception: If the PWM duty cycle = 0%, the pin will not be set.) • The PWM duty cycle is latched from CCPR1L into CCPR1H. The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle.
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PIC16F631/677/685/687/689/690 11.3.4 OPERATION IN SLEEP MODE In Sleep mode, the TMR2 register will not increment and the state of the module will not change. If the CCP1 pin is driving a value, it will continue to drive that value. When the device wakes up, TMR2 will continue from its previous state. 11.3.5 CHANGES IN SYSTEM CLOCK FREQUENCY The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will result in changes to the PWM frequency. See Section 3.
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PIC16F631/677/685/687/689/690 FIGURE 11-5: EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE Duty Cycle Registers DC1B<1:0> CCP1M<3:0> 4 P1M<1:0> 2 CCPR1L CCP1/P1A CCP1/P1A TRIS CCPR1H (Slave) P1B R Comparator Output Controller Q P1B TRIS P1C TMR2 (1) Clear Timer2, toggle PWM pin and latch duty cycle PR2 1: TRIS S P1D Comparator Note P1C P1D TRIS PWM1CON The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 1
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PIC16F631/677/685/687/689/690 FIGURE 11-6: EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) P1M<1:0> Signal PR2+1 Pulse Width 0 Period 00 (Single Output) P1A Modulated Delay(1) Delay(1) P1A Modulated 10 (Half-Bridge) P1B Modulated P1A Active 01 (Full-Bridge, Forward) P1B Inactive P1C Inactive P1D Modulated P1A Inactive 11 (Full-Bridge, Reverse) P1B Modulated P1C Active P1D Inactive Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Pulse Width =
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PIC16F631/677/685/687/689/690 FIGURE 11-7: EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) Signal P1M<1:0> PR2+1 Pulse Width 0 Period 00 (Single Output) P1A Modulated P1A Modulated 10 (Half-Bridge) Delay(1) Delay(1) P1B Modulated P1A Active 01 (Full-Bridge, Forward) P1B Inactive P1C Inactive P1D Modulated P1A Inactive 11 (Full-Bridge, Reverse) P1B Modulated P1C Active P1D Inactive Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Pulse Width = TOSC * (
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PIC16F631/677/685/687/689/690 11.4.1 HALF-BRIDGE MODE In Half-Bridge mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the CCP1/P1A pin, while the complementary PWM output signal is output on the P1B pin (see Figure 11-6). This mode can be used for Half-Bridge applications, as shown in Figure 11-9, or for Full-Bridge applications, where four power switches are being modulated with two PWM signals.
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PIC16F631/677/685/687/689/690 11.4.2 FULL-BRIDGE MODE In Full-Bridge mode, all four pins are used as outputs. An example of Full-Bridge application is shown in Figure 11-10. In the Forward mode, pin CCP1/P1A is driven to its active state, pin P1D is modulated, while P1B and P1C will be driven to their inactive state as shown in Figure 11-11. In the Reverse mode, P1C is driven to its active state, pin P1B is modulated, while P1A and P1D will be driven to their inactive state as shown Figure 11-11.
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PIC16F631/677/685/687/689/690 FIGURE 11-11: EXAMPLE OF FULL-BRIDGE PWM OUTPUT Forward Mode Period P1A (2) Pulse Width P1B(2) P1C(2) P1D(2) (1) (1) Reverse Mode Period Pulse Width P1A(2) P1B(2) P1C(2) P1D(2) (1) Note 1: 2: (1) At this time, the TMR2 register is equal to the PR2 register. Output signal is shown as active-high. DS41262E-page 138 © 2008 Microchip Technology Inc.
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PIC16F631/677/685/687/689/690 11.4.2.1 Direction Change in Full-Bridge Mode In the Full-Bridge mode, the P1M1 bit in the CCP1CON register allows users to control the forward/reverse direction. When the application firmware changes this direction control bit, the module will change to the new direction on the next PWM cycle. A direction change is initiated in software by changing the P1M1 bit of the CCP1CON register.
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PIC16F631/677/685/687/689/690 FIGURE 11-13: EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE Forward Period t1 Reverse Period P1A P1B PW P1C P1D PW TON External Switch C TOFF External Switch D Potential Shoot-Through Current Note 1: 11.4.3 T = TOFF – TON All signals are shown as active-high. 2: TON is the turn on delay of power switch QC and its driver. 3: TOFF is the turn off delay of power switch QD and its driver.
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PIC16F631/677/685/687/689/690 11.4.4 ENHANCED PWM AUTO-SHUTDOWN MODE A shutdown condition is indicated by the ECCPASE (Auto-Shutdown Event Status) bit of the ECCPAS register. If the bit is a ‘0’, the PWM pins are operating normally. If the bit is a ‘1’, the PWM outputs are in the shutdown state. The PWM mode supports an Auto-Shutdown mode that will disable the PWM outputs when an external shutdown event occurs. Auto-Shutdown mode places the PWM output pins into a predetermined state.
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PIC16F631/677/685/687/689/690 REGISTER 11-2: ECCPAS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ECCPASE: ECCP Auto-Shutdown Event Status bit 1 = A shutdown event has occurred; ECCP outputs
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PIC16F631/677/685/687/689/690 FIGURE 11-15: PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PRSEN = 0) Shutdown Event ECCPASE bit PWM Activity PWM Period Start of PWM Period 11.4.5 ECCPASE Cleared by Shutdown Shutdown Firmware PWM Event Occurs Event Clears Resumes AUTO-RESTART MODE The Enhanced PWM can be configured to automatically restart the PWM signal once the auto-shutdown condition has been removed. Auto-restart is enabled by setting the PRSEN bit in the PWM1CON register.
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PIC16F631/677/685/687/689/690 11.4.6 PROGRAMMABLE DEAD-BAND DELAY MODE FIGURE 11-17: In Half-Bridge applications where all power switches are modulated at the PWM frequency, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on, and the other turned off), both switches may be on for a short period of time until one switch completely turns off.
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PIC16F631/677/685/687/689/690 REGISTER 11-3: PWM1CON: ENHANCED PWM CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes away; the PWM restart
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PIC16F631/677/685/687/689/690 11.4.7 PULSE STEERING MODE In Single Output mode, pulse steering allows any of the PWM pins to be the modulated signal. Additionally, the same PWM signal can be simultaneously available on multiple pins.
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PIC16F631/677/685/687/689/690 FIGURE 11-19: SIMPLIFIED STEERING BLOCK DIAGRAM STRA P1A Signal CCP1M1 1 PORT Data 0 P1A pin STRB CCP1M0 1 PORT Data 0 STRC CCP1M1 1 PORT Data 0 TRIS P1B pin TRIS P1C pin TRIS STRD CCP1M0 1 PORT Data 0 P1D pin TRIS Note 1: Port outputs are configured as shown when the CCP1CON register bits P1M<1:0> = 00 and CCP1M<3:2> = 11. 2: Single PWM output requires setting at least one of the STRx bits. © 2008 Microchip Technology Inc.
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PIC16F631/677/685/687/689/690 11.4.7.1 Steering Synchronization The STRSYNC bit of the PSTRCON register gives the user two selections of when the steering event will happen. When the STRSYNC bit is ‘0’, the steering event will happen at the end of the instruction that writes to the PSTRCON register. In this case, the output signal at the P1 pins may be an incomplete PWM waveform. This operation is useful when the user firmware needs to immediately remove a PWM signal from the pin.
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PIC16F631/677/685/687/689/690 TABLE 11-5: Name SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND PWM Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CM1CON0 C1ON C1OUT C1OE C1POL — C1R C1CH1 C2ON C2OUT C2OE C2POL — C2R C2CH1 — — — — T1GSS CM2CON0 Bit 0 Value on POR, BOR Value on all other Resets CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000 C1CH0 0000 -000 0000 -000 C2CH0 0000 -000 0000 -000 CM2CON1 MC1OUT MC2OUT C2SYNC 00-- --10
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PIC16F631/677/685/687/689/690 12.
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PIC16F631/677/685/687/689/690 FIGURE 12-2: EUSART RECEIVE BLOCK DIAGRAM SPEN CREN RX/DT pin Baud Rate Generator Data Recovery FOSC BRG16 SPBRGH SPBRG Multiplier x4 x16 x64 SYNC 1 X 0 0 0 BRGH X 1 1 0 0 BRG16 X 1 0 1 0 Stop RCIDL RSR Register MSb Pin Buffer and Control +1 OERR (8) ••• 7 1 LSb 0 START RX9 ÷n n FERR RX9D RCREG Register 8 FIFO Data Bus RCIF RCIE Interrupt The operation of the EUSART module is controlled through three registers: • Transmit Status and Cont
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PIC16F631/677/685/687/689/690 12.1 EUSART Asynchronous Mode The EUSART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is implemented with two levels: a VOH mark state which represents a ‘1’ data bit, and a VOL space state which represents a ‘0’ data bit. NRZ refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission.
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PIC16F631/677/685/687/689/690 12.1.1.4 TSR Status 12.1.1.6 The TRMT bit of the TXSTA register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXREG. The TRMT bit remains clear until all bits have been shifted out of the TSR register. No interrupt logic is tied to this bit, so the user has to poll this bit to determine the TSR status. Note: 12.1.1.5 1. 2. 3.
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PIC16F631/677/685/687/689/690 TABLE 12-1: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Name Bit 7 Bit 6 BAUDCTL ABDOVF GIE INTCON PIE1 PIR1 RCREG Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00 RABIE T0IF INTF RABIF 0000 000x 0000 000x TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000 TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000 0000 0000 0000 0000 Bit 5 Bit 4 Bit 3 RCIDL — SCKP PEIE T0IE INT
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PIC16F631/677/685/687/689/690 12.1.2 EUSART ASYNCHRONOUS RECEIVER The Asynchronous mode is typically used in RS-232 systems. The receiver block diagram is shown in Figure 12-2. The data is received on the RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate.
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PIC16F631/677/685/687/689/690 12.1.2.4 Receive Framing Error Each character in the receive FIFO buffer has a corresponding framing error Status bit. A framing error indicates that a Stop bit was not seen at the expected time. The framing error status is accessed via the FERR bit of the RCSTA register. The FERR bit represents the status of the top unread character in the receive FIFO. Therefore, the FERR bit must be read before reading the RCREG.
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PIC16F631/677/685/687/689/690 12.1.2.8 1. 2. 3. 4. 5. 6. 7. 8. 9. Asynchronous Reception Set-up: 12.1.2.9 Initialize the SPBRGH, SPBRG register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 12.3 “EUSART Baud Rate Generator (BRG)”). Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register.
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PIC16F631/677/685/687/689/690 TABLE 12-2: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Name Bit 7 Bit 6 BAUDCTL ABDOVF GIE INTCON PIE1 PIR1 RCREG Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00 RABIE T0IF INTF RABIF 0000 000x 0000 000x TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000 TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000 0000 0000 0000 0000 Bit 5 Bit 4 Bit 3 RCIDL — SCKP PEIE T0IE INTE
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PIC16F631/677/685/687/689/690 12.2 Clock Accuracy with Asynchronous Operation The factory calibrates the internal oscillator block output (INTOSC). However, the INTOSC frequency may drift as VDD or temperature changes, and this directly affects the asynchronous baud rate. Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind. REGISTER 12-1: The first (preferred) method uses the OSCTUNE register to adjust the INTOSC output.
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PIC16F631/677/685/687/689/690 REGISTER 12-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in
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PIC16F631/677/685/687/689/690 REGISTER 12-3: BAUDCTL: BAUD RATE CONTROL REGISTER R-0 R-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode: 1 = Auto-baud timer overflowed 0 = Auto-baud timer did not overflow Synchronous mode: Don’t care
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PIC16F631/677/685/687/689/690 12.3 EUSART Baud Rate Generator (BRG) The Baud Rate Generator (BRG) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous EUSART operation. By default, the BRG operates in 8-bit mode. Setting the BRG16 bit of the BAUDCTL register selects 16-bit mode. If the system clock is changed during an active receive operation, a receive error or data loss may result.
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PIC16F631/677/685/687/689/690 TABLE 12-5: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE FOSC = 20.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 18.432 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 11.0592 MHz Actual Rate % Error FOSC = 8.000 MHz SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 300 — — — — — — — — — — — — 1200 1221 1.73 255 1200 0.00 239 1200 0.00 143 1202 0.16 103 2400 2404 0.
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PIC16F631/677/685/687/689/690 TABLE 12-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz Actual Rate % Error SPBRG value (decimal) 300 1200 — 1202 — 0.16 — 207 — 1200 — 0.00 — 191 — 1202 — 0.16 — 103 300 1202 0.16 0.16 207 51 2400 2404 0.16 103 2400 0.00 95 2404 0.16 51 2404 0.
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PIC16F631/677/685/687/689/690 TABLE 12-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz FOSC = 8.000 MHz Actual Rate % Error SPBRG value (decimal) 300 1200 300.0 1200 0.00 -0.01 16665 4166 300.0 1200 0.00 0.00 15359 3839 300.0 1200 0.00 0.00 9215 2303 300.0 1200 0.00 -0.02 6666 1666 2400 2400 0.02 2082 2400 0.00 1919 2400 0.00 1151 2401 0.
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PIC16F631/677/685/687/689/690 12.3.1 AUTO-BAUD DETECT The EUSART module supports automatic detection and calibration of the baud rate. In the Auto-Baud Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RX signal, the RX signal is timing the BRG. The Baud Rate Generator is used to time the period of a received 55h (ASCII “U”) which is the Sync character for the LIN bus.
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PIC16F631/677/685/687/689/690 12.3.2 AUTO-WAKE-UP ON BREAK During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator is inactive and a proper character reception cannot be performed. The Auto-Wake-up feature allows the controller to wake-up due to activity on the RX/DT line. This feature is available only in Asynchronous mode. The Auto-Wake-up feature is enabled by setting the WUE bit of the BAUDCTL register.
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PIC16F631/677/685/687/689/690 FIGURE 12-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 OSC1 Auto Cleared Bit Set by User WUE bit RX/DT Line Note 1 RCIF Sleep Command Executed Note 1: 2: 12.3.3 If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is still active. This sequence should not depend on the presence of Q clocks.
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PIC16F631/677/685/687/689/690 FIGURE 12-9: Write to TXREG SEND BREAK CHARACTER SEQUENCE Dummy Write BRG Output (Shift Clock) TX (pin) Start bit bit 0 bit 1 bit 11 Stop bit Break TXIF bit (Transmit Interrupt Flag) TRMT bit (Transmit Shift Empty Flag) SENDB (send Break control bit) DS41262E-page 170 SENDB Sampled Here Auto Cleared © 2008 Microchip Technology Inc.
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PIC16F631/677/685/687/689/690 12.4 EUSART Synchronous Mode Synchronous serial communications are typically used in systems with a single master and one or more slaves. The master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. There are two signal lines in Synchronous mode: a bidirectional data line and a clock line.
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PIC16F631/677/685/687/689/690 FIGURE 12-10: SYNCHRONOUS TRANSMISSION RX/DT pin bit 0 bit 1 Word 1 bit 2 bit 7 bit 0 bit 1 Word 2 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to TXREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit TXEN bit ‘1’ Note: ‘1’ Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words.
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PIC16F631/677/685/687/689/690 12.4.1.5 Synchronous Master Reception Data is received at the RX/DT pin. The RX/DT pin output driver is automatically disabled when the EUSART is configured for synchronous master receive operation. In Synchronous mode, reception is enabled by setting either the Single Receive Enable bit (SREN of the RCSTA register) or the Continuous Receive Enable bit (CREN of the RCSTA register).
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PIC16F631/677/685/687/689/690 FIGURE 12-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RXREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
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PIC16F631/677/685/687/689/690 12.4.2 SYNCHRONOUS SLAVE MODE The following bits are used to configure the EUSART for Synchronous slave operation: • • • • • SYNC = 1 CSRC = 0 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 1. 2. 3. 4. Setting the SYNC bit of the TXSTA register configures the device for synchronous operation. Clearing the CSRC bit of the TXSTA register configures the device as a slave.
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PIC16F631/677/685/687/689/690 12.4.2.3 EUSART Synchronous Slave Reception 12.4.2.4 The operation of the Synchronous Master and Slave modes is identical (Section 12.4.1.5 “Synchronous Master Reception”), with the following exceptions: • Sleep • CREN bit is always set, therefore the receiver is never Idle • SREN bit, which is a “don't care” in Slave mode A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep.
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PIC16F631/677/685/687/689/690 12.5 EUSART Operation During Sleep The EUSART WILL remain active during Sleep only in the Synchronous Slave mode. All other modes require the system clock and therefore cannot generate the necessary signals to run the Transmit or Receive Shift registers during Sleep. Synchronous Slave mode uses an externally generated clock to run the Transmit and Receive Shift registers. 12.5.
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PIC16F631/677/685/687/689/690 13.0 SSP MODULE OVERVIEW FIGURE 13-1: The Synchronous Serial Port (SSP) module is a serial interface used to communicate with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc.
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PIC16F631/677/685/687/689/690 REGISTER 13-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER(1) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: SPI Data Input Sample Phase bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time (Micr
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PIC16F631/677/685/687/689/690 REGISTER 13-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3(2) SSPM2(2) SSPM1(2) SSPM0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (m
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PIC16F631/677/685/687/689/690 13.2 Operation When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON<5:0> and SSPSTAT<7:6>).
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PIC16F631/677/685/687/689/690 13.3 Enabling SPI I/O 13.4 To enable the serial port, SSP Enable bit SSPEN of the SSPCON register must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, re-initialize the SSPCON registers and then set the SSPEN bit. This configures the SDI, SDO, SCK and SS pins as serial port pins. For the pins to behave as the serial port function, some must have their data direction bits (in the TRISB and TRISC registers) appropriately programmed.
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PIC16F631/677/685/687/689/690 13.5 Master Mode The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 13-2) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input).
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PIC16F631/677/685/687/689/690 13.6 Slave Mode In Slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. While in Sleep mode, the slave can transmit/receive data.
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PIC16F631/677/685/687/689/690 FIGURE 13-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 SDI (SMP = 0) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF FIGURE 13-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO SDI (SMP = 0) bit 6 bit 7 bit 7 bit 5 bit 4 bit 3 bit
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PIC16F631/677/685/687/689/690 13.8 Sleep Operation 13.10 Bus Mode Compatibility In Master mode, all module clocks are halted and the transmission/reception will remain in that state until the device wakes from Sleep. After the device returns to Normal mode, the module will continue to transmit/ receive data. Table 13-1 shows the compatibility between the standard SPI modes and the states of the CKP and CKE control bits.
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PIC16F631/677/685/687/689/690 13.11 SSP I2C Operation The SSP module in I2C mode, fully implements all slave functions, except general call support, and provides interrupts on Start and Stop bits in hardware to facilitate firmware implementations of the master functions. The SSP module implements the Standard mode specifications, as well as 7-bit and 10-bit addressing. Two pins are used for data transfer.
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PIC16F631/677/685/687/689/690 13.12.1 ADDRESSING Once the SSP module has been enabled, it waits for a Start condition to occur. Following the Start condition, the 8-bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register. The address is compared on the falling edge of the eighth clock (SCL) pulse.
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PIC16F631/677/685/687/689/690 13.12.2 RECEPTION When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register. When the address byte overflow condition exists, then no Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF of the SSPSTAT register is set, or bit SSPOV of the SSPCON register is set. This is an error condition due to the user’s firmware.
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PIC16F631/677/685/687/689/690 13.12.3 SSP MASK REGISTER 2 An SSP Mask (SSPMSK) register is available in I C Slave mode as a mask for the value held in the SSPSR register during an address comparison operation. A zero (‘0’) bit in the SSPMSK register has the effect of making the corresponding bit in the SSPSR register a ‘don’t care’. This register is reset to all ‘1’s upon any Reset condition and, therefore, has no effect on standard SSP operation until written with a mask value.
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DS41262E-page 192 3 5 6 8 UA is set indicating that the SSPADD needs to be updated 9 A7 (CKP does not reset to ‘0’ when SEN = 0) UA (SSPSTAT<1>) 7 SSPBUF is written with contents of SSPSR SSPOV (SSPCON<6>) CKP 4 Cleared in software BF (SSPSTAT<0>) (PIR1<3>) SSPIF 2 1 SCL S SDA 2 4 5 6 7 Cleared in software 3 8 UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with low byte of address Dummy read of SSPBUF to clear BF flag 1 A6 A5
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PIC16F631/677/685/687/689/690 13.12.4 TRANSMISSION An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF must be cleared in software, and the SSPSTAT register is used to determine the status of the byte. Flag bit SSPIF is set on the falling edge of the ninth clock pulse. When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register.
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DS41262E-page 194 1 3 5 6 8 UA is set indicating that the SSPADD needs to be updated 9 (CKP does not reset to ‘0’ when SEN = 0) UA (SSPSTAT<1>) 7 SSPBUF is written with contents of SSPSR SSPOV (SSPCON<6>) CKP 4 Cleared in software 2 BF (SSPSTAT<0>) (PIR1<3>) SSPIF S 2 4 5 6 7 Cleared in software 3 8 UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with low byte of address Dummy read of SSPBUF to clear BF flag 1 9 1 4 5 6 7 Cl
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PIC16F631/677/685/687/689/690 13.13 Master Mode 13.14 Multi-Master Mode Master mode of operation is supported in firmware using interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the SSP module is disabled. The Stop (P) and Start (S) bits will toggle based on the Start and Stop conditions. Control of the I2C bus may be taken when the P bit is set or the bus is idle and both the S and P bits are clear.
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PIC16F631/677/685/687/689/690 FIGURE 13-12: CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDA DX DX-1 SCL Master device asserts clock CKP Master device deasserts clock WR SSPCON TABLE 13-4: Addr REGISTERS ASSOCIATED WITH I2C™ OPERATION(1) Value on all other Resets Value on POR, BOR Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0Bh/8Bh/ INTCON 10Bh/18Bh GIE PEIE T0IE INTE RABIE T0IF INTF RABIF 0000 000x
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PIC16F631/677/685/687/689/690 14.0 SPECIAL FEATURES OF THE CPU The PIC16F631/677/685/687/689/690 have a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving features and offer code protection.
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PIC16F631/677/685/687/689/690 14.1 Configuration Bits The Configuration bits can be programmed (read as ‘0’), or left unprogrammed (read as ‘1’) to select various device configurations as shown in Register 14-2. These bits are mapped in program memory location 2007h. Note: Address 2007h is beyond the user program memory space. It belongs to the special configuration memory space (2000h3FFFh), which can be accessed only during programming.
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PIC16F631/677/685/687/689/690 REGISTER 14-1: Reserved CONFIG: CONFIGURATION WORD REGISTER Reserved FCMEN BOREN1(1) IESO BOREN0(1) bit 13 CPD(2 bit 7 CP(3) MCLRE(4) PWRTE WDTE FOSC2 FOSC1 bit 6 FOSC0 bit 0 Legend: R = Readable bit W = Writable bit P = Programmable’ U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 13-12 Reserved: Reserved bits. Do Not Use.
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PIC16F631/677/685/687/689/690 14.2 Reset The PIC16F631/677/685/687/689/690 differentiates between various kinds of Reset: a) b) c) d) e) f) Power-on Reset (POR) WDT Reset during normal operation WDT Reset during Sleep MCLR Reset during normal operation MCLR Reset during Sleep Brown-out Reset (BOR) Some registers are not affected in any Reset condition; their status is unknown on POR and unchanged in any other Reset.
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PIC16F631/677/685/687/689/690 14.2.1 POWER-ON RESET (POR) FIGURE 14-2: The on-chip POR circuit holds the chip in Reset until VDD has reached a high enough level for proper operation. A maximum rise time for VDD is required. See Section 17.0 “Electrical Specifications” for details. If the BOR is enabled, the maximum rise time specification does not apply. The BOR circuitry will keep the device in Reset until VDD reaches VBOR (see Section 14.2.4 “Brown-out Reset (BOR)”).
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PIC16F631/677/685/687/689/690 14.2.4 BROWN-OUT RESET (BOR) On any Reset (Power-on, Brown-out Reset, Watchdog Timer, etc.), the chip will remain in Reset until VDD rises above VBOR (see Figure 14-3). The Power-up Timer will now be invoked, if enabled and will keep the chip in Reset an additional 64 ms. The BOREN0 and BOREN1 bits in the Configuration Word register select one of four BOR modes. Two modes have been added to allow software or hardware control of the BOR enable.
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PIC16F631/677/685/687/689/690 14.2.5 TIME-OUT SEQUENCE 14.2.6 On power-up, the time-out sequence is as follows: first, PWRT time-out is invoked after POR has expired, then OST is activated after the PWRT time-out has expired. The total time-out will vary based on oscillator configuration and PWRTE bit status. For example, in EC mode with PWRTE bit erased (PWRT disabled), there will be no time-out at all. Figures 14-4, 14-5 and 14-6 depict time-out sequences.
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PIC16F631/677/685/687/689/690 FIGURE 14-4: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1 VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2 FIGURE 14-5: VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset FIGURE 14-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD) VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset DS41262E-page 204 © 2008 Microchip Technology Inc.
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PIC16F631/677/685/687/689/690 TABLE 14-4: Register W INITIALIZATION CONDITION FOR REGISTER Address Power-on Reset MCLR Reset WDT Reset Brown-out Reset(1) Wake-up from Sleep through Interrupt Wake-up from Sleep through WDT Time-out — xxxx xxxx uuuu uuuu uuuu uuuu INDF 00h/80h/ 100h/180h xxxx xxxx xxxx xxxx uuuu uuuu TMR0 01h/101h xxxx xxxx uuuu uuuu uuuu uuuu PCL 02h/82h/ 102h/182h 0000 0000 0000 0000 PC + 1(3) STATUS 03h/83h/ 103h/183h 0001 1xxx 000q quuu(4) uuuq quuu(4) FSR
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PIC16F631/677/685/687/689/690 TABLE 14-4: INITIALIZATION CONDITION FOR REGISTER (CONTINUED) Wake-up from Sleep through Interrupt Wake-up from Sleep through WDT Time-out Address Power-on Reset MCLR Reset WDT Reset (Continued) Brown-out Reset(1) TRISB 86h/186h 1111 ---- 1111 ---- uuuu ---- TRISC Register 87h/187h 1111 1111 1111 1111 uuuu uuuu PIE1 8Ch -000 0000 -000 0000 -uuu uuuu PIE2 8Dh 0000 ---- 0000 ---- uuuu uuuu 1, 5) PCON 8Eh --01 --0x OSCCON 8Fh -110 q000 -110 q000 -
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PIC16F631/677/685/687/689/690 TABLE 14-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS Program Counter Status Register PCON Register Power-on Reset 000h 0001 1xxx --01 --0x MCLR Reset during normal operation 000h 000u uuuu --0u --uu MCLR Reset during Sleep 000h 0001 0uuu --0u --uu Condition WDT Reset WDT Wake-up Brown-out Reset Interrupt Wake-up from Sleep 000h 0000 uuuu --0u --uu PC + 1 uuu0 0uuu --uu --uu 000h 0001 1uuu --01 --u0 uuu1 0uuu --uu --uu PC + 1 (1) Legend: u =
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PIC16F631/677/685/687/689/690 14.
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PIC16F631/677/685/687/689/690 14.3.2 TIMER0 INTERRUPT 14.3.3 An overflow (FFh → 00h) in the TMR0 register will set the T0IF (INTCON<2>) bit. The interrupt can be enabled/disabled by setting/clearing T0IE (INTCON<5>) bit. See Section 5.0 “Timer0 Module” for operation of the Timer0 module. PORTA/PORTB INTERRUPT An input change on PORTA or PORTB change sets the RABIF (INTCON<0>) bit. The interrupt can be enabled/ disabled by setting/clearing the RABIE (INTCON<3>) bit.
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PIC16F631/677/685/687/689/690 FIGURE 14-8: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT (3) (4) INT pin (1) (1) INTF flag (INTCON<1>) Interrupt Latency (2) (5) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction Fetched INTCON Inst (0004h) Inst (0005h) Dummy Cycle Inst (0004h) — Dummy Cycle Inst (PC) 0005h INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency = 3-4 TCY.
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PIC16F631/677/685/687/689/690 14.4 Context Saving During Interrupts During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt (e.g., W and STATUS registers). This must be implemented in software. Since the upper 16 bytes of all GPR banks are common in the PIC16F631/677/685/687/689/690 (see Figures 2-2 and 2-3), temporary holding registers, W_TEMP and STATUS_TEMP, should be placed in here.
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PIC16F631/677/685/687/689/690 14.5 Watchdog Timer (WDT) 14.5.2 The WDT has the following features: • • • • • Operates from the LFINTOSC (31 kHz) Contains a 16-bit prescaler Shares an 8-bit prescaler with Timer0 Time-out period is from 1 ms to 268 seconds Configuration bit and software controlled WDT is cleared under certain conditions described in Table 14-7. 14.5.1 WDT OSCILLATOR The WDT derives its time base from the 31 kHz LFINTOSC.
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PIC16F631/677/685/687/689/690 REGISTER 14-2: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 U-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4-1 WDTPS<3:0>: Watchdog Timer Period Select bits Bit Value = Prescale Rate 0000 = 1:32 0001 = 1:64 0010 = 1:128 0011 = 1:256 01
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PIC16F631/677/685/687/689/690 14.6 Power-Down Mode (Sleep) The Power-down mode is entered by executing a SLEEP instruction. If the Watchdog Timer is enabled: • • • • • WDT will be cleared but keeps running. PD bit in the STATUS register is cleared. TO bit is set. Oscillator driver is turned off. I/O ports maintain the status they had before SLEEP was executed (driving high, low or highimpedance).
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PIC16F631/677/685/687/689/690 FIGURE 14-10: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(2) CLKOUT(4) INT pin INTF flag (INTCON<1>) Interrupt Latency (3) GIE bit (INTCON<7>) Instruction Flow PC Instruction Fetched Instruction Executed Note 14.7 Processor in Sleep PC Inst(PC) = Sleep Inst(PC – 1) PC + 1 PC + 2 Inst(PC + 1) Inst(PC + 2) Sleep Inst(PC + 1) 14.
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PIC16F631/677/685/687/689/690 FIGURE 14-11: TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION To Normal Connections External Connector Signals PIC16F631/677/ 685/687/689/690 * +5V VDD 0V VSS VPP RA3/MCLR/VPP CLK RA1 Data I/O RA0 * * * To Normal Connections * Isolation devices (as required) DS41262E-page 216 © 2008 Microchip Technology Inc.
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PIC16F631/677/685/687/689/690 15.0 INSTRUCTION SET SUMMARY The PIC16F690 instruction set is highly orthogonal and is comprised of three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations Each PIC16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction.
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PIC16F631/677/685/687/689/690 TABLE 15-2: PIC16F684 INSTRUCTION SET Mnemonic, Operands Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f – f, d f, d f, d f, d f, d f, d f, d f – f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR
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PIC16F631/677/685/687/689/690 15.2 Instruction Descriptions ADDLW Add literal and W Syntax: [ label ] ADDLW BCF k Operands: 0 ≤ k ≤ 255 Operation: (W) + k → (W) Status Affected: C, DC, Z Description: The contents of the W register are added to the eight-bit literal ‘k’ and the result is placed in the W register.
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PIC16F631/677/685/687/689/690 BTFSS Bit Test f, Skip if Set CLRWDT Clear Watchdog Timer Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRWDT Operands: 0 ≤ f ≤ 127 0≤b<7 Operands: None Operation: Operation: skip if (f) = 1 Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘0’, the next instruction is executed. If bit ‘b’ is ‘1’, then the next instruction is discarded and a NOP is executed instead, making this a two-cycle instruction.
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PIC16F631/677/685/687/689/690 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) - 1 → (destination); skip if result = 0 Operation: (f) + 1 → (destination), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in the W register.
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PIC16F631/677/685/687/689/690 MOVWF Move W to f Syntax: [ label ] MOVF Move f Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 Operation: (W) → (f) Operation: (f) → (dest) Status Affected: None Status Affected: Z Description: Description: The contents of register ‘f’ is moved to a destination dependent upon the status of ‘d’. If d = 0, destination is W register. If d = 1, the destination is file register ‘f’ itself.
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PIC16F631/677/685/687/689/690 RETFIE Return from Interrupt RETLW Return with literal in W Syntax: [ label ] Syntax: [ label ] RETFIE RETLW k Operands: None Operands: 0 ≤ k ≤ 255 Operation: TOS → PC, 1 → GIE Operation: k → (W); TOS → PC Status Affected: None Status Affected: None Description: Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction.
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PIC16F631/677/685/687/689/690 RLF Rotate Left f through Carry SLEEP Enter Sleep mode Syntax: [ label ] Syntax: [ label ] SLEEP Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: None Operation: Operation: See description below Status Affected: C Description: The contents of register ‘f’ are rotated one bit to the left through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’.
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PIC16F631/677/685/687/689/690 SUBWF Subtract W from f XORLW Exclusive OR literal with W Syntax: [ label ] SUBWF f,d Syntax: [ label ] XORLW k Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ k ≤ 255 Operation: (f) - (W) → (destination) (W) .XOR. k → (W) Status Affected: Z Description: The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register.
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PIC16F631/677/685/687/689/690 16.
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PIC16F631/677/685/687/689/690 16.2 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging.
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PIC16F631/677/685/687/689/690 16.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment.
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PIC16F631/677/685/687/689/690 16.11 PICSTART Plus Development Programmer 16.13 Demonstration, Development and Evaluation Boards The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins.
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PIC16F631/677/685/687/689/690 17.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings(†) Ambient temperature under bias..........................................................................................................-40° to +125°C Storage temperature ........................................................................................................................ -65°C to +150°C Voltage on VDD with respect to VSS ..............................................................................
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PIC16F631/677/685/687/689/690 FIGURE 17-1: PIC16F631/677/685/687/689/690 VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C 5.5 5.0 VDD (V) 4.5 4.0 3.5 3.0 2.5 2.0 0 8 10 20 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE FIGURE 17-2: 125 ± 5% Temperature (°C) 85 ± 2% 60 ± 1% 25 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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PIC16F631/677/685/687/689/690 17.1 DC Characteristics: PIC16F631/677/685/687/689/690-I (Industrial) PIC16F631/677/685/687/689/690-E (Extended) DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No. Min. Typ† Max. Units Sym Characteristic Conditions VDD Supply Voltage 2.0 2.0 3.0 4.5 — — — — 5.5 5.5 5.5 5.
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PIC16F631/677/685/687/689/690 17.2 DC Characteristics: PIC16F631/677/685/687/689/690-I (Industrial) PIC16F631/677/685/687/689/690-E (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended DC CHARACTERISTICS Param No. Device Characteristics Supply Current (IDD) D010 D011* D012 D013* D014 D015 D016* D017 D018 D019 † Note 1: 2: 3: 4: 5: (1, 2) Min. Typ† Max.
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PIC16F631/677/685/687/689/690 17.2 DC Characteristics: PIC16F631/677/685/687/689/690-I (Industrial) PIC16F631/677/685/687/689/690-E (Extended) (Continued) DC CHARACTERISTICS Param No. Device Characteristics D020 Power-down Base Current(IPD)(2) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Min. Typ† Max. Units Conditions VDD — 0.05 1.2 μA 2.0 — 0.15 1.5 μA 3.0 — 0.35 1.8 μA 5.
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PIC16F631/677/685/687/689/690 17.3 DC Characteristics: PIC16F631/677/685/687/689/690-E (Extended) DC CHARACTERISTICS Param No. Device Characteristics D020E Power-down Base Current(IPD)(2) D021E D022E D023E D024E D024AE* Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Conditions Min. Typ† Max. Units — 0.05 9 μA 2.0 — 0.15 11 μA 3.0 — 0.35 15 μA 5.0 — 90 500 nA 3.
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PIC16F631/677/685/687/689/690 17.4 DC Characteristics: PIC16F631/677/685/687/689/690-I (Industrial) PIC16F631/677/685/687/689/690-E (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended DC CHARACTERISTICS Param No. Sym. VIL Characteristic Min. Typ† Max. Units Vss Vss Conditions — 0.8 V 4.5V ≤ VDD ≤ 5.5V — 0.15 VDD V 2.0V ≤ VDD ≤ 4.5V Vss — 0.2 VDD V 2.0V ≤ VDD ≤ 5.5V 0.
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PIC16F631/677/685/687/689/690 17.4 DC Characteristics: PIC16F631/677/685/687/689/690-I (Industrial) PIC16F631/677/685/687/689/690-E (Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended DC CHARACTERISTICS Param No. Sym. D100 IULP Characteristic Min. Typ† Max.
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PIC16F631/677/685/687/689/690 17.5 Thermal Considerations Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Param No. TH01 TH02 TH03 TH04 TH05 TH06 TH07 Note 1: 2: 3: Sym. θJA Characteristic Thermal Resistance Junction to Ambient Typ. Units 62.4 85.2 108.1 40 28.1 24.2 32.2 2.
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PIC16F631/677/685/687/689/690 17.6 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2.
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PIC16F631/677/685/687/689/690 17.7 AC Characteristics: PIC16F631/677/685/687/689/690 (Industrial, Extended) FIGURE 17-4: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1/CLKIN OS02 OS04 OS04 OS03 OSC2/CLKOUT (LP,XT,HS Modes) OSC2/CLKOUT (CLKOUT Mode) TABLE 17-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Param No. Sym.
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PIC16F631/677/685/687/689/690 TABLE 17-2: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No. Sym. Characteristic Freq. Tolerance Min. Typ† Max. Units Conditions OS06 TWARM Internal Oscillator Switch when running(3) — — — 2 TOSC Slowest clock OS07 TSC Fail-Safe Sample Clock Period(1) — — 21 — ms LFINTOSC/64 OS08 HFOSC Internal Calibrated HFINTOSC Frequency(2) ±1% 7.92 8.0 8.08 MHz VDD = 3.
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PIC16F631/677/685/687/689/690 FIGURE 17-5: CLKOUT AND I/O TIMING Cycle Write Fetch Read Execute Q4 Q1 Q2 Q3 FOSC OS12 OS11 OS20 OS21 CLKOUT OS19 OS18 OS16 OS13 OS17 I/O pin (Input) OS14 OS15 I/O pin (Output) New Value Old Value OS18, OS19 TABLE 17-3: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No. Sym. Characteristic Min. Typ† Max.
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PIC16F631/677/685/687/689/690 FIGURE 17-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Start-up Time Internal Reset(1) Watchdog Timer Reset(1) 31 34 34 I/O pins Note 1: Asserted low.
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PIC16F631/677/685/687/689/690 TABLE 17-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No. Sym. Characteristic Min. Typ† Max.
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PIC16F631/677/685/687/689/690 FIGURE 17-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 49 47 TMR0 or TMR1 TABLE 17-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No. 40* Sym.
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PIC16F631/677/685/687/689/690 FIGURE 17-9: CAPTURE/COMPARE/PWM TIMINGS (ECCP) CCP1 (Capture mode) CC01 CC02 CC03 Note: TABLE 17-6: Refer to Figure 17-3 for load conditions. CAPTURE/COMPARE/PWM REQUIREMENTS (ECCP) Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No. CC01* CC02* CC03* Sym. TccL TccH TccP Characteristic CCP1 Input Low Time CCP1 Input High Time CCP1 Input Period Min. Typ† Max. Units No Prescaler 0.
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PIC16F631/677/685/687/689/690 TABLE 17-7: COMPARATOR SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Comparator Specifications Param. No. Sym. Characteristics Min. Typ. Max. Units CM01 VOS Input Offset Voltage — ± 5.0 ± 10 mV CM02 VCM Input Common Mode Voltage 0 — VDD - 1.
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PIC16F631/677/685/687/689/690 FIGURE 17-10: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RB7/TX/CK pin 121 121 RB5/AN11/RX/DT pin 120 Note: 122 Refer to Figure 17-3 for load conditions. TABLE 17-10: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param. No.
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PIC16F631/677/685/687/689/690 FIGURE 17-12: SPI MASTER MODE TIMING (CKE = 0, SMP = 0) SS 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 bit 6 - - - - - -1 MSb SDO LSb 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 73 Note: Refer to Figure 17-3 for load conditions.
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PIC16F631/677/685/687/689/690 FIGURE 17-14: SPI SLAVE MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 83 71 72 78 79 79 78 SCK (CKP = 1) 80 MSb SDO LSb bit 6 - - - - - -1 77 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 73 Note: Refer to Figure 17-3 for load conditions.
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PIC16F631/677/685/687/689/690 TABLE 17-12: SPI MODE REQUIREMENTS Param No. Symbol Characteristic TSSL2SCH, SS↓ to SCK↓ or SCK↑ input TSSL2SCL 70* Min. Typ† Max.
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PIC16F631/677/685/687/689/690 TABLE 17-13: I2C™ BUS START/STOP BITS REQUIREMENTS Param No. Symbol Characteristic 90* TSU:STA 91* THD:STA 92* TSU:STO 93 THD:STO Stop condition Start condition 100 kHz mode 4700 Typ. Max. Units — — Setup time 400 kHz mode 600 — — Start condition 100 kHz mode 4000 — — Hold time 400 kHz mode 600 — — Stop condition 100 kHz mode 4700 — — Setup time Hold time * Min.
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PIC16F631/677/685/687/689/690 TABLE 17-14: I2C™ BUS DATA REQUIREMENTS Param. No. 100* Symbol THIGH Characteristic Clock high time Min. Max. Units 100 kHz mode 4.0 — μs Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — μs Device must operate at a minimum of 10 MHz 1.5TCY — 100 kHz mode 4.7 — μs Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — μs Device must operate at a minimum of 10 MHz 1.
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PIC16F631/677/685/687/689/690 TABLE 17-15: A/D CONVERTER (ADC) CHARACTERISTICS: Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Param Sym. No. Characteristic Min. Typ† Max. Units Conditions AD01 NR Resolution — — 10 bits AD02 EIL Integral Error — — ±1 LSb VREF = 5.12V AD03 EDL Differential Error — — ±1 LSb No missing codes to 10 bits VREF = 5.12V AD04 EOFF Offset Error AD04A — — ±1 — +1.5 +3.0 bit LSb VREF = 5.
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PIC16F631/677/685/687/689/690 FIGURE 17-18: A/D CONVERSION TIMING (NORMAL MODE) BSF ADCON0, GO 1 TCY (TOSC/2)(1) 134 131 Q4 130 A/D CLK 9 A/D Data 8 7 3 6 2 1 0 NEW_DATA OLD_DATA ADRES 1 TCY ADIF GO DONE Note 1: Sampling Stopped 132 Sample If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
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PIC16F631/677/685/687/689/690 FIGURE 17-19: A/D CONVERSION TIMING (SLEEP MODE) BSF ADCON0, GO 134 (TOSC/2 + TCY)(1) 1 TCY 131 Q4 130 A/D CLK 9 A/D Data 8 7 6 OLD_DATA ADRES 3 2 1 0 NEW_DATA ADIF 1 TCY GO DONE Sample Note 1: 132 Sampling Stopped If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. © 2008 Microchip Technology Inc.
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PIC16F631/677/685/687/689/690 TABLE 1: A/D CONVERSION REQUIREMENTS (SLEEP MODE) Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No. 130* Sym. TAD Characteristic A/D Internal RC Oscillator Period Min. Typ† Max. Units Conditions 3.0* 6.0 9.0* μs ADCS<1:0> = 11 (RC mode) At VDD = 2.5V At VDD = 5.0V 2.0* 4.0 6.0* μs 131 TCNV Conversion Time (not including Acquisition Time)(1) — 11 — TAD 132* TACQ Acquisition Time (2) 11.
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PIC16F631/677/685/687/689/690 18.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range.
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PIC16F631/677/685/687/689/690 FIGURE 18-2: MAXIMUM IDD vs. FOSC OVER VDD (EC MODE) EC Mode 4.0 3.5 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 5.5V 5.0V 3.0 IDD (mA) 2.5 4.0V 2.0 3.0V 1.5 2.0V 1.0 0.5 0.0 1 MHz 2 MHz 4 MHz 6 MHz 8 MHz 10 MHz 12 MHz 14 MHz 16 MHz 18 MHz 20 MHz FOSC FIGURE 18-3: TYPICAL IDD vs. FOSC OVER VDD (HS MODE) Typical IDD vs FOSC Over Vdd HS Mode 4.0 3.
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PIC16F631/677/685/687/689/690 FIGURE 18-4: MAXIMUM IDD vs. FOSC OVER VDD (HS MODE) Maximum IDD vs FOSC Over Vdd HS Mode 5.0 4.5 4.0 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 5.5V IDD (mA) 3.5 5.0V 3.0 4.5V 2.5 2.0 1.5 4.0V 3.5V 3.0V 1.0 0.5 0.0 4 MHz 10 MHz 16 MHz 20 MHz FOSC FIGURE 18-5: TYPICAL IDD vs.
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PIC16F631/677/685/687/689/690 FIGURE 18-6: MAXIMUM IDD vs. VDD OVER FOSC (XT MODE) XT Mode 1,400 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 1,200 1,000 IDD (μA) 800 4 MHz 600 400 1 MHz 200 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-7: IDD vs. VDD (LP MODE) 80 70 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) IDD (uA) 60 50 32 kHz Maximum 40 30 32 kHz Typical 20 10 0 2.0 2.5 3.0 4.0 3.
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PIC16F631/677/685/687/689/690 FIGURE 18-8: TYPICAL IDD vs. VDD OVER FOSC (EXTRC MODE) EXTRC Mode 800 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 700 600 IDD (μA) 500 4 MHz 400 300 1 MHz 200 100 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 5.0 5.5 VDD (V) MAXIMUM IDD vs.
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PIC16F631/677/685/687/689/690 FIGURE 18-10: IDD vs. VDD OVER FOSC (LFINTOSC MODE, 31 kHz) LFINTOSC Mode, 31KHZ 80 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 70 60 IDD (μA) 50 Maximum 40 30 Typical 20 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-11: VDD (HFINTOSC MODE) TYPICAL IDD vs. FOSC OVER HFINTOSC 1,600 1,400 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 5.5V 5.
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PIC16F631/677/685/687/689/690 FIGURE 18-12: MAXIMUM IDD vs. FOSC OVER VDD (HFINTOSC MODE) HFINTOSC 2,000 1,800 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 5.5V 5.0V 1,600 1,400 4.0V IDD (μA) 1,200 1,000 3.0V 800 600 2.0V 400 200 0 125 kHz 250 kHz 500 kHz 1 MHz 2 MHz 4 MHz 8 MHz FOSC FIGURE 18-13: TYPICAL IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) Typical (Sleep Mode all Peripherals Disabled) 0.45 0.40 0.
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PIC16F631/677/685/687/689/690 FIGURE 18-14: MAXIMUM IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) Maximum (Sleep Mode all Peripherals Disabled) 18.0 16.0 Typical: Statistical Mean @25°C Maximum: Mean + 3σ Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 14.0 Max. 125°C IPD (μA) 12.0 10.0 8.0 6.0 4.0 Max. 85°C 2.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-15: COMPARATOR IPD vs.
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PIC16F631/677/685/687/689/690 FIGURE 18-16: BOR IPD vs. VDD OVER TEMPERATURE 160 140 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 120 IPD (μA) 100 Maximum 80 Typical 60 40 20 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-17: TYPICAL WDT IPD vs. VDD OVER TEMPERATURE Typical 3.0 2.5 Typical: Statistical StatisticalMean Mean @25°C @25°C Typical: Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) IPD (μA) 2.0 1.5 1.0 0.5 0.0 2.0 2.5 3.0 3.
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PIC16F631/677/685/687/689/690 FIGURE 18-18: MAXIMUM WDT IPD vs. VDD OVER TEMPERATURE Maximum 25.0 20.0 IPD (μA) Max. 125°C 15.0 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 10.0 Max. 85°C 5.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-19: WDT PERIOD vs. VDD OVER TEMPERATURE 30 28 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) Max. (125°C) 26 Max.
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PIC16F631/677/685/687/689/690 FIGURE 18-20: WDT PERIOD vs. TEMPERATURE OVER VDD (5.0V) Vdd = 5V 30 28 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 26 Maximum 24 Time (ms) 22 20 Typical 18 16 Minimum 14 12 10 -40°C 25°C 85°C 125°C Temperature (°C) FIGURE 18-21: CVREF IPD vs. VDD OVER TEMPERATURE (HIGH RANGE) High Range 140 120 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 100 IPD (μA) Max. 125°C 80 Max.
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PIC16F631/677/685/687/689/690 FIGURE 18-22: CVREF IPD vs. VDD OVER TEMPERATURE (LOW RANGE) 180 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 160 140 120 IPD (μA) Max. 125°C 100 Max. 85°C 80 Typical 60 40 20 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-23: TYPICAL VP6 REFERENCE IPD vs. VDD (25°C) VP6 Reference IPD vs. VDD (25×C) 160 140 IPD (uA) 120 100 Typical 80 60 40 20 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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PIC16F631/677/685/687/689/690 FIGURE 18-24: MAXIMUM VP6 REFERENCE IPD vs. VDD OVER TEMPERATURE Max VP6 Reference IPD vs. VDD Over Temperature 180 160 140 Max 125°C IPD (uA) 120 Max 85°C 100 80 60 40 20 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 5.0 5.5 VDD (V) FIGURE 18-25: T1OSC IPD vs. VDD OVER TEMPERATURE (32 kHz) 30 25 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) Max. 125°C IPD (uA) 20 15 10 5 2 2.5 3 3.5 4 4.5 5 5.5 Typ 25×C 2.022 2.247 2.
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PIC16F631/677/685/687/689/690 FIGURE 18-26: VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V) (VDD = 3V, -40×C TO 125×C) 0.8 0.7 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) Max. 125°C 0.6 VOL (V) 0.5 Max. 85°C 0.4 Typical 25°C 0.3 0.2 Min. -40°C 0.1 0.0 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 IOL (mA) VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V) FIGURE 18-27: 0.
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PIC16F631/677/685/687/689/690 FIGURE 18-28: VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V) 3.5 3.0 Max. -40°C Typ. 25°C 2.5 Min. 125°C VOH (V) 2.0 1.5 1.0 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 0.5 0.0 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 IOH (mA) FIGURE 18-29: (VDD = 5.0V) VOH vs. IOH OVER TEMPERATURE ( , ) 5.5 5.0 Max. -40°C Typ. 25°C VOH (V) 4.5 Min. 125°C 4.0 3.
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PIC16F631/677/685/687/689/690 FIGURE 18-30: TTL INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE (TTL Input, -40×C TO 125×C) 1.7 1.5 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) Max. -40°C VIN (V) 1.3 Typ. 25°C 1.1 Min. 125°C 0.9 0.7 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-31: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE (ST Input, -40×C TO 125×C) 4.0 VIH Max. 125°C 3.
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PIC16F631/677/685/687/689/690 FIGURE 18-32: COMPARATOR RESPONSE TIME (RISING EDGE) 531 806 1000 900 Max. 125°C Response Time (nS) 800 700 600 Note: 500 VCM = VDD - 1.5V)/2 V+ input = VCM V- input = Transition from VCM + 100MV to VCM - 20MV Max. 85°C 400 300 Typ. 25°C 200 Min. -40°C 100 0 2.0 2.5 4.0 5.5 VDD (V) FIGURE 18-33: COMPARATOR RESPONSE TIME (FALLING EDGE) 1000 900 Max. 125°C 800 Response Time (nS) 700 600 500 Note: VCM = VDD - 1.
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PIC16F631/677/685/687/689/690 FIGURE 18-34: LFINTOSC FREQUENCY vs. VDD OVER TEMPERATURE (31 kHz) LFINTOSC 31Khz 45,000 40,000 Max. -40°C 35,000 Typ. 25°C Frequency (Hz) 30,000 25,000 20,000 Min. 85°C Min. 125°C 15,000 10,000 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 5,000 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-35: ADC CLOCK PERIOD vs.
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PIC16F631/677/685/687/689/690 FIGURE 18-36: TYPICAL HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE 16 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 14 85°C 12 25°C Time (μs) 10 -40°C 8 6 4 2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-37: MAXIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE -40C to +85C 25 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) Time (μs) 20 15 85°C 25°C 10 -40°C 5 0 2.
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PIC16F631/677/685/687/689/690 FIGURE 18-38: MINIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE -40C to +85C 10 9 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 8 Time (μs) 7 85°C 6 25°C 5 -40°C 4 3 2 1 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-39: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (25°C) 5 4 Change from Calibration (%) 3 2 1 0 -1 -2 -3 -4 -5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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PIC16F631/677/685/687/689/690 FIGURE 18-40: TYPICAL HFINTOSC FREQUENCY CHANGE OVER DEVICE VDD (85°C) 5 4 Change from Calibration (%) 3 2 1 0 -1 -2 -3 -4 -5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-41: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (125°C) 5 4 Change from Calibration (%) 3 2 1 0 -1 -2 -3 -4 -5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) © 2008 Microchip Technology Inc.
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PIC16F631/677/685/687/689/690 FIGURE 18-42: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (-40°C) 5 4 Change from Calibration (%) 3 2 1 0 -1 -2 -3 -4 -5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-43: TYPICAL VP6 REFERENCE VOLTAGE vs. VDD (25°C) VP6 Reference Voltage vs. VDD (25×C) 0.65 0.64 0.63 VP6 (V) 0.62 0.61 0.60 0.59 Typical 0.58 0.57 0.56 0.55 2 3 4 5 5.5 VDD (V) DS41262E-page 280 © 2008 Microchip Technology Inc.
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PIC16F631/677/685/687/689/690 FIGURE 18-44: TYPICAL VP6 REFERENCE VOLTAGE OVER TEMPERATURE (3V) Typical VP6 Reference Voltage vs. Temperature (VDD=3V) 0.66 0.64 Max. VP6 (V) 0.62 0.6 Typical 0.58 Min. 0.56 0.54 0.52 -40°C 25°C 85°C 125°C Temperature (°C) FIGURE 18-45: TYPICAL VP6 REFERENCE VOLTAGE OVER TEMPERATURE (5V) Typical VP6 Reference Voltage vs. Temperature (VDD=5V) 0.66 0.64 VP6 (V) 0.62 Max. 0.6 Typical 0.58 0.56 Min. 0.54 0.
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PIC16F631/677/685/687/689/690 FIGURE 18-46: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (3V, 25°C) Typical VP6 Reference Voltage Distribution (VDD=3V, 25×C) 35 Parts=118 Number of Parts 30 25 20 15 10 5 0.690 0.700 0.690 0.700 0.680 0.670 0.660 0.650 0.640 0.630 0.620 0.610 0.600 0.590 0.580 0.570 0.560 0.550 0.540 0.530 0.520 0.510 0.
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PIC16F631/677/685/687/689/690 FIGURE 18-48: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (3V, 125°C) Typical VP6 Reference Voltage Distribution (VDD=3V, 125×C) 40 35 Parts=118 Number of Parts 30 25 20 15 10 5 0.700 0.690 0.680 0.670 0.660 0.650 0.640 0.630 0.620 0.610 0.600 0.590 0.580 0.570 0.560 0.550 0.540 0.530 0.520 0.510 0.
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PIC16F631/677/685/687/689/690 FIGURE 18-50: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (5V, 25°C) Typical VP6 Reference Voltage Distribution (VDD=5V, 25×C) 30 Number of Parts 25 Parts=118 20 15 10 5 0.700 0.690 0.680 0.670 0.660 0.650 0.640 0.630 0.620 0.610 0.600 0.590 0.580 0.570 0.560 0.550 0.540 0.530 0.520 0.510 0.
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PIC16F631/677/685/687/689/690 FIGURE 18-52: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (5V, 125°C) Typical VP6 Reference Voltage Distribution (VDD=5V, 25×C) 30 25 Number of Parts Parts=118 20 15 10 5 0.700 0.690 0.680 0.670 0.660 0.650 0.640 0.630 0.620 0.610 0.600 0.590 0.580 0.570 0.560 0.550 0.540 0.530 0.520 0.510 0.
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PIC16F631/677/685/687/689/690 19.0 PACKAGING INFORMATION 19.1 Package Marking Information 20-Lead PDIP Example PIC16F685-I/P e3 0710017 XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 20-Lead SOIC (7.50 mm) XXXXXXXXXXXXXX XXXXXXXXXXXXXX XXXXXXXXXXXXXX Example PIC16F685-I /SO e3 0710017 YYWWNNN 20-Lead SSOP Example XXXXXXXXXXX XXXXXXXXXXX YYWWNNN 20-Lead QFN Example XXXXXX XXXXXX YWWNNN Legend: XX...
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PIC16F631/677/685/687/689/690 19.2 Package Details The following sections give the technical details of the packages.
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PIC16F631/677/685/687/689/690 /HDG 3ODVWLF 6PDOO 2XWOLQH 62 ± :LGH PP %RG\ >62,&@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D N E E1 NOTE 1 1 2 3 e b α h h A A2 c φ L A1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV β L1 0,//,0(7(56 0,1 1 120 0$; 3LWFK H 2YHUDOO +HLJKW $ ± %6& ± 0ROGHG 3DFNDJH 7KLFNQHVV $ ± ± 6WDQGRII $ ± 2YHUDOO :LGWK ( 0ROGH
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PIC16F631/677/685/687/689/690 /HDG 3ODVWLF 6KULQN 6PDOO 2XWOLQH 66 ± PP %RG\ >6623@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D N E E1 NOTE 1 1 2 b e c A2 A φ A1 L1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV L 0,//,0(7(56 0,1 1 120 0$; 3LWFK H 2YHUDOO +HLJKW $ ± %6& ± 0ROGHG 3DFNDJH 7KLFNQHVV $ 6WDQGRII $ ± ± 2YHUDOO :LGWK (
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PIC16F631/677/685/687/689/690 /HDG 3ODVWLF 4XDG )ODW 1R /HDG 3DFNDJH 0/ ± [ [ PP %RG\ >4)1@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D D2 EXPOSED PAD e E2 2 E b 2 1 1 K N N NOTE 1 TOP VIEW L BOTTOM VIEW A A1 A3 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 0,//,0(7(56 0,1 1 120 0$; 3LWFK H 2YHUDOO +HLJKW $ 6WDQGRII $ &RQWDFW 7KLFNQHVV
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PIC16F631/677/685/687/689/690 APPENDIX A: DATA SHEET REVISION HISTORY Revision A (March 2005) APPENDIX B: MIGRATING FROM OTHER PIC® DEVICES This is a new data sheet. This discusses some of the issues in migrating from other PIC devices to the PIC16F6XX Family of devices. Revision B (May 2006) B.1 Added 631/677 part numbers; Added pin summary tables after pin diagrams; Incorporated Golden Chapters. TABLE B-1: Revision C (July 2006) Revised Section 4.2.
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PIC16F631/677/685/687/689/690 INDEX A A/D Specifications............................................ 255, 256, 257 Absolute Maximum Ratings .............................................. 231 AC Characteristics Industrial and Extended ............................................ 241 Load Conditions ........................................................ 240 ACK pulse ......................................................................... 188 ADC ............................................................
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PIC16F631/677/685/687/689/690 CKP bit .............................................................................. 181 Clock Accuracy with Asynchronous Operation ................. 160 Clock Sources External Modes ........................................................... 49 EC ....................................................................... 49 HS ....................................................................... 50 LP........................................................................
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PIC16F631/677/685/687/689/690 Baud Rate Error, Calculating ............................ 163 Baud Rates, Asynchronous Modes .................. 164 Formulas ........................................................... 163 High Baud Rate Select (BRGH Bit) .................. 163 Synchronous Master Mode ............................... 171, 175 Associated Registers Receive..................................................... 174 Transmit.................................................... 172 Reception............
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PIC16F631/677/685/687/689/690 Oscillator Associated registers.............................................. 58, 89 Oscillator Module ................................................................ 47 EC ............................................................................... 47 HFINTOSC.................................................................. 47 HS ............................................................................... 47 INTOSC ......................................................
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PIC16F631/677/685/687/689/690 IOCB (Interrupt-on-Change PORTB) .......................... 70 OPTION_REG (OPTION) ..................................... 37, 83 OSCCON (Oscillator Control) ..................................... 48 OSCTUNE (Oscillator Tuning) .................................... 52 PCON (Power Control Register) ................................. 43 PCON (Power Control) ............................................. 203 PIE1 (Peripheral Interrupt Enable 1)...........................
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PIC16F631/677/685/687/689/690 T2CON................................................................ 92 Timing Diagrams A/D Conversion ......................................................... 256 A/D Conversion (Sleep Mode) .................................. 257 Asynchronous Reception .......................................... 158 Asynchronous Transmission ..................................... 154 Asynchronous Transmission (Back to Back) ............ 154 Auto Wake-up Bit (WUE) During Normal Operation .
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PIC16F631/677/685/687/689/690 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
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PIC16F631/677/685/687/689/690 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
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PIC16F631/677/685/687/689/690 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Device Temperature Range Package Pattern Examples: a) b) Device: PIC16F631(1), PIC16F677(1), PIC16F685(1), PIC16F687(1), PIC16F689(1), PIC16F690(1); VDD range 2.0V to 5.
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WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.