Information

PIC16F631/677/685/687/689/690
DS80243M-page 8  2010 Microchip Technology Inc.
FIGURE 8-3: COMPARATOR C2 SIMPLIFIED BLOCK DIAGRAM
FIGURE 1: SILICON REVISION A4 AND PREVIOUS VS. REVISION A5
MUX
C2
C2POL
C2OUT
0
1
2
3
C2ON
(1)
C2CH<1:0>
2
From TMR1
Clock
DQ
EN
DQ
EN
CL
DQ
RD_CM2CON0
Q3*RD_CM2CON0
Q1
Set C2IF
To
NRESET
C2V
IN-
C2V
IN+
C12IN0-
C12IN1-
C2IN2-
C2IN3-
0
1
C2SYNC
C2POL
Data Bus
MUX
Note 1: When C2ON = 0, the C2 comparator will produce a ‘0’ output to the XOR Gate.
2: Q1 and Q3 are phases of the four-phase system clock (F
OSC).
3: Q1 is held high during Sleep mode.
0
1
C2R
CV
REF
MUX
C2IN+
0
1
MUX
SYNCC2OUT
to Timer1 Gate, SR latch
C2V
REN
FixedRef
and other peripherals
Rev. A4 and previous:
To ECCP Auto-Shutdown
Rev. A5: To ECCP
Auto-Shutdown
A4 and previous revisions
Rev. A5 CCP Output
CxOUT
CxIF
Uncertainty due to
Q1 cycle delay
Uncertainty due to
Q1 cycle delay
Read CMxCON0
Read CMxCON0
CCP Output