Datasheet

PIC16F688
DS41203E-page 82 © 2009 Microchip Technology Inc.
FIGURE 9-1: FLASH PROGRAM MEMORY READ CYCLE EXECUTION
TABLE 9-1: SUMMARY OF REGISTERS ASSOCIATED WITH DATA EEPROM
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Value on
all other
Resets
EECON1 EEPGD
— — — WRERR WREN WR RD x--- x000 0--- q000
EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- ---- ----
EEADR EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000
EEADRH
— — — — EEADRH3 EEADRH2 EEADRH1 EEADRH0 ---- 0000 ---- 0000
EEDAT EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000
EEDATH
— — EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0 --00 0000 --00 0000
INTCON GIE PEIE T0IE
INTE RABIE T0IF INTF RABIF 0000 000x 0000 000x
PIE1
EEIE ADIE RCIE C2IE C1IE OSFIE TXIE TMR1IE
0000 0000 0000 0000
PIR1
EEIF ADIF RCIF C2IF C1IF OSFIF TXIF TMR1IF
0000 0000 0000 0000
Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends upon condition.
Shaded cells are not used by data EEPROM module.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
BSF EECON1,RD
executed here
INSTR(PC + 1)
executed here
Forced NOP
executed here
PC
PC + 1 EEADRH,EEADR
PC+3
PC + 5
Flash ADDR
RD bit
EEDATH,EEDAT
PC + 3 PC + 4
INSTR (PC + 1)
INSTR(PC - 1)
executed here
INSTR(PC + 3)
executed here
INSTR(PC + 4)
executed here
Flash Data
EEDATH
EEDAT
Register
EERHLT
INSTR (PC) INSTR (PC + 3) INSTR (PC + 4)