Datasheet

© 2009 Microchip Technology Inc. DS41203E-page 11
PIC16F688
TABLE 2-3: PIC16F688 SPECIAL REGISTERS SUMMARY BANK 2
AddrNameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2 Bit 1Bit 0
Value on
POR/BOR
Page
Bank 2
100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 20, 117
101h TMR0 Timer0 Module’s register xxxx xxxx 45, 117
102h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 19, 117
103h STATUS IRP RP1 RP0 TO
PD ZDCC0001 1xxx 13, 117
104h FSR Indirect Data Memory Address Pointer xxxx xxxx 20, 117
105h PORTA
RA5 RA4 RA3 RA2 RA1 RA0 --x0 x000
33, 117
106h Unimplemented
107h PORTC
RC5 RC4 RC3 RC2 RC1 RC0 --xx 0000 42, 117
108h Unimplemented
109h Unimplemented
10Ah PCLATH
Write Buffer for upper 5 bits of Program Counter ---0 0000 19, 117
10Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF
(2)
0000 000x 15, 117
10Ch Unimplemented
10Dh Unimplemented
10Eh Unimplemented
10Fh Unimplemented
110h Unimplemented
111h Unimplemented
112h Unimplemented
113h Unimplemented
114h Unimplemented
115h Unimplemented
116h Unimplemented
117h Unimplemented
118h Unimplemented
119h Unimplemented
11Ah Unimplemented
11Bh Unimplemented
11Ch Unimplemented
11Dh Unimplemented
11Eh Unimplemented
11Fh Unimplemented
Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: Other (non Power-up) Resets include MCLR
Reset and Watchdog Timer Reset during normal operation.
2: MCLR
and WDT Reset does not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set again if the
mismatched exists.