Datasheet
© 2009 Microchip Technology Inc. DS41203E-page 9
PIC16F688
TABLE 2-1: PIC16F688 SPECIAL REGISTERS SUMMARY BANK 0
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR/BOR
Page
Bank 0
00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 20, 117
01h TMR0 Timer0 Module’s register xxxx xxxx
45, 117
02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000
19, 117
03h STATUS IRP RP1 RP0 TO
PD ZDCC0001 1xxx 13, 117
04h FSR Indirect Data Memory Address Pointer xxxx xxxx
20, 117
05h PORTA
— — RA5 RA4 RA3 RA2 RA1 RA0 --x0 x000
33, 117
06h — Unimplemented — —
07h PORTC
— — RC5 RC4 RC3 RC2 RC1 RC0 --xx 0000 42, 117
08h — Unimplemented — —
09h — Unimplemented — —
0Ah PCLATH
— — — Write Buffer for upper 5 bits of Program Counter ---0 0000
19, 117
0Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF
(2)
0000 000x 15, 117
0Ch PIR1
EEIF ADIF RCIF C2IF C1IF OSFIF TXIF TMR1IF 0000 0000 17, 117
0Dh — Unimplemented — —
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 xxxx xxxx
48, 117
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 xxxx xxxx
48, 117
10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR1CS TMR1ON 0000 0000 51, 117
11h BAUDCTL ABDOVF RCIDL
— SCKP BRG16 —WUEABDEN01-0 0-00 94, 117
12h SPBRGH USART Baud Rate High Generator 0000 0000 95, 117
13h SPBRG USART Baud Rate Generator 0000 0000 95, 117
14h RCREG USART Receive Register 0000 0000 87, 117
15h TXREG USART Transmit Register 0000 0000 87, 117
16h TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 92, 117
17h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 93, 117
18h WDTCON
— — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 124, 117
19h CMCON0 C2OUT C1OUT
C2INV C1INV CIS CM2 CM1 CM0 0000 0000 61, 117
1Ah CMCON1
— — — — — — T1GSS C2SYNC ---- --10 62, 117
1Bh — Unimplemented — —
1Ch — Unimplemented — —
1Dh — Unimplemented — —
1Eh ADRESH Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result xxxx xxxx
72, 117
1Fh ADCON0 ADFM VCFG
— CHS2 CHS1 CHS0 GO/DONE ADON 00-0 0000
71, 117
Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: Other (non Power-up) Resets include MCLR
Reset and Watchdog Timer Reset during normal operation.
2: MCLR
and WDT Reset does not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set again if the
mismatched exists.