Datasheet

PIC16F688
DS41203E-page 106 © 2009 Microchip Technology Inc.
FIGURE 10-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
TABLE 10-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
NameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Value on
POR, BOR
Value on
all other
Resets
BAUDCTL
ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00
INTCON
GIE PEIE T0IE INTE RAIE T0IF INTF RAIF
0000 000x 0000 000x
PIE1
EEIE ADIE RCIE C2IE C1IE OSFIE TXIE TMR1IE
0000 0000 0000 0000
PIR1
EEIF ADIF RCIF C2IF C1IF OSFIF TXIF TMR1IF
0000 0000 0000 0000
RCREG EUSART Receive Data Register 0000 0000 0000 0000
RCSTA SPEN RX9 SREN CREN
ADDEN FERR OERR RX9D 0000 000x 0000 000x
SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000
SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 0000 0000 0000 0000
TRISC
— — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111
--11 1111
TXREG EUSART Transmit Data Register 0000 0000 0000 0000
TXSTA
CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010
Legend: x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Master Reception.
CREN bit
RX/DT
Write to
bit SREN
SREN bit
RCIF bit
(Interrupt)
Read
RXREG
‘0’
bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
‘0’
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TX/CK pin
TX/CK pin
pin
(SCKP = 0)
(SCKP = 1)