PIC16F688 Data Sheet 14-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology © 2009 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC16F688 14-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology High-Performance RISC CPU: Low-Power Features: • Only 35 Instructions to Learn: - All single-cycle instructions except branches • Operating Speed: - DC – 20 MHz oscillator/clock input - DC – 200 ns instruction cycle • Interrupt Capability • 8-level Deep Hardware Stack • Direct, Indirect and Relative Addressing modes • Standby Current: - 50 nA @ 2.0V, typical • Operating Current: - 11 μA @ 32 kHz, 2.
PIC16F688 Program Memory Data Memory Device Flash (words) SRAM (bytes) EEPROM (bytes) 4096 256 256 PIC16F688 I/O 10-bit A/D (ch) Comparators Timers 8/16-bit 12 8 2 1/1 Pin Diagram (PDIP, SOIC, TSSOP) 14-pin PDIP, SOIC, TSSOP 1 14 VSS RA5/T1CKI/OSC1/CLKIN 2 13 RA0/AN0/C1IN+/ICSPDAT/ULPWU RA4/AN3/T1G/OSC2/CLKOUT 3 12 RA1/AN1/C1IN-/VREF/ICSPCLK RA3/MCLR/VPP 4 11 RA2/AN2/T0CKI/INT/C1OUT RC5/RX/DT 5 10 RC0/AN4/C2IN+ RC4/C2OUT/TX/CK 6 9 RC1/AN5/C2IN- RC3/AN7 7 8 RC2/AN6
PIC16F688 Pin Diagram (QFN) TABLE 2: NC VSS 14 13 2 NC RA4/AN3/T1G/OSC2/CLKOUT 15 1 VDD RA5/T1CKI/OSC1/CLKIN 16 16-pin QFN PIC16F688 12 RA0/AN0/C1IN+/ICSPDAT/ULPWU 11 RA1/AN1/C1IN-/VREF/ICSPCLK RA2/AN2/T0CKI/INT/C1OUT 7 8 RC1/AN5/C2IN- 9 RC2/AN6 4 6 RC5/RX/DT RC3/AN7 10 5 3 RC4/C2OUT/TX/CK RA3/MCLR/VPP RC0/AN4/C2IN+ PIC16F688 16-PIN SUMMARY (QFN) I/O Pin Analog Comparators Timers EUSART Interrupt Pull-up Basic RA0 12 AN0/ULPWU C1IN+ — — IOC Y ICSPDAT RA1 1
PIC16F688 Table of Contents 1.0 Device Overview ......................................................................................................................................................................... 5 2.0 Memory Organization .................................................................................................................................................................. 7 3.0 Clock Sources .....................................................................................
PIC16F688 1.0 DEVICE OVERVIEW The PIC16F688 is covered by this data sheet. It is available in 14-pin PDIP, SOIC, TSSOP and QFN packages. Figure 1-1 shows a block diagram of the PIC16F688 device. Table 1-1 shows the pinout description.
PIC16F688 TABLE 1-1: PIC16F688 PINOUT DESCRIPTION Name Function Input Type Output Type RA0/AN0/C1IN+/ICSPDAT/ULPWU RA0 TTL CMOS AN0 AN — A/D Channel 0 input C1IN+ AN — Comparator 1 input ICSPDAT TTL CMOS ULPWU AN — RA1 TTL CMOS RA1/AN1/C1IN-/VREF/ICSPCLK RA2/AN2/T0CKI/INT/C1OUT RA3/MCLR/VPP RA4/AN3/T1G/OSC2/CLKOUT RA5/T1CKI/OSC1/CLKIN RC0/AN4/C2IN+ RC1/AN5/C2IN- RC2/AN6 RC3/AN7 RC4/C2OUT/TX/CK RC5/RX/DT Description PORTA I/O w/prog pull-up and interrupt-on-change Serial P
PIC16F688 2.0 MEMORY ORGANIZATION 2.1 Program Memory Organization The PIC16F688 has a 13-bit program counter capable of addressing a 4K x 14 program memory space. Only the first 4K x 14 (0000h-01FFF) for the PIC16F688 is physically implemented. Accessing a location above these boundaries will cause a wrap-around within the first 4K x 14 space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure 2-1).
PIC16F688 FIGURE 2-2: PIC16F688 SPECIAL FUNCTION REGISTERS File Address Indirect addr. (1) 00h TMR0 01h PCL 02h STATUS 03h FSR 04h PORTA 05h 06h PORTC 07h 08h 09h PCLATH 0Ah INTCON 0Bh PIR1 0Ch 0Dh TMR1L 0Eh TMR1H 0Fh T1CON 10h BAUDCTL 11h SPBRGH 12h SPBRG 13h RCREG 14h TXREG 15h TXSTA 16h RCSTA 17h WDTCON 18h CMCON0 19h CMCON1 1Ah 1Bh 1Ch 1Dh ADRESH 1Eh ADCON0 1Fh 20h File Address Indirect addr.
PIC16F688 TABLE 2-1: Addr Name PIC16F688 SPECIAL REGISTERS SUMMARY BANK 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR/BOR Page Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 20, 117 01h TMR0 Timer0 Module’s register xxxx xxxx 45, 117 02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 19, 117 03h STATUS 13, 117 04h FSR 05h PORTA 06h 07h IRP RP1 TO PD Z DC C 0001 1x
PIC16F688 TABLE 2-2: Addr PIC16F688 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR/BOR Page xxxx xxxx 20, 117 1111 1111 14, 117 Bank 1 80h INDF 81h OPTION_REG 82h PCL 83h STATUS 84h FSR 85h TRISA RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Program Counter’s (PC) Least Significant Byte IRP RP1 — TRISC — — — 19, 117 13, 117 PD Z DC C 0001 1xxx xxxx xxxx 20, 117 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
PIC16F688 TABLE 2-3: Addr Name PIC16F688 SPECIAL REGISTERS SUMMARY BANK 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR/BOR Page Bank 2 100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 20, 117 101h TMR0 Timer0 Module’s register xxxx xxxx 45, 117 102h PCL Program Counter’s (PC) Least Significant Byte 103h STATUS 104h FSR 105h PORTA 106h — 107h IRP RP1 RP0 TO PD Z DC C RA4 RA3 RA2 RA1
PIC16F688 TABLE 2-4: Addr PIC16F688 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR/BOR Page xxxx xxxx 20, 117 Bank 3 180h INDF 181h OPTION_REG 182h PCL 183h STATUS 184h FSR 185h TRISA 186h 187h Addressing this location uses contents of FSR to address data memory (not a physical register) RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Program Counter’s (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C Indirect
PIC16F688 2.2.2.1 STATUS Register The STATUS register, shown in Register 2-1, contains: • the arithmetic status of the ALU • the Reset status • the bank select bits for data memory (SRAM) The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic.
PIC16F688 2.2.2.2 OPTION Register Note: The OPTION register is a readable and writable register, which contains various control bits to configure: • • • • Timer0/WDT prescaler External RA2/INT interrupt Timer0 Weak pull-ups on PORTA REGISTER 2-2: To achieve a 1:1 prescaler assignment for Timer0, assign the prescaler to the WDT by setting PSA bit of the OPTION register to ‘1’. See Section 5.1.3 “Software Programmable Prescaler”.
PIC16F688 2.2.2.3 INTCON Register Note: The INTCON register is a readable and writable register, which contains the various enable and flag bits for TMR0 register overflow, PORTA change and external RA2/INT pin interrupts. REGISTER 2-3: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE of the INTCON register.
PIC16F688 2.2.2.4 PIE1 Register The PIE1 register contains the interrupt enable bits, as shown in Register 2-4. REGISTER 2-4: Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.
PIC16F688 2.2.2.5 PIR1 Register The PIR1 register contains the interrupt flag bits, as shown in Register 2-5. REGISTER 2-5: Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE bit of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC16F688 2.2.2.6 PCON Register The Power Control (PCON) register (see Register 2-6) contains flag bits to differentiate between a: • • • • Power-on Reset (POR) Brown-out Reset (BOR) Watchdog Timer Reset (WDT) External MCLR Reset The PCON register also controls the Ultra Low-Power Wake-up and software enable of the BOR.
PIC16F688 2.3 2.3.2 PCL and PCLATH The Program Counter (PC) is 13 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 2-3 shows the two situations for the loading of the PC. The upper example in Figure 2-3 shows how the PC is loaded on a write to PCL (PCLATH<4:0> → PCH).
PIC16F688 2.4 Indirect Addressing, INDF and FSR Registers A simple program to clear RAM location 20h-2Fh using indirect addressing is shown in Example 2-1. The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. EXAMPLE 2-1: MOVLW MOVWF NEXT CLRF INCF BTFSS GOTO CONTINUE Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses data pointed to by the File Select Register (FSR).
PIC16F688 3.0 OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR) The oscillator module can be configured in one of eight clock modes. 3.1 Overview 1. 2. 3. The oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 3-1 illustrates a block diagram of the oscillator module. 4. 5.
PIC16F688 3.2 Oscillator Control The Oscillator Control (OSCCON) register (Figure 3-1) controls the system clock and frequency selection options.
PIC16F688 3.3 Clock Source Modes Clock source modes can be classified as external or internal. External Clock Modes 3.4.1 OSCILLATOR START-UP TIMER (OST) If the oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) counts 1024 oscillations from OSC1. This occurs following a Power-on Reset (POR) and when the Power-up Timer (PWRT) has expired (if configured), or a wake-up from Sleep.
PIC16F688 3.4.3 LP, XT, HS MODES The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure 3-3). The mode selects a low, medium or high gain setting of the internal inverteramplifier to support various resonator types and speed. LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current consumption is the least of the three modes.
PIC16F688 3.4.4 EXTERNAL RC MODES 3.5 The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. There are two modes: RC and RCIO. In RC mode, the RC circuit connects to OSC1. OSC2/ CLKOUT outputs the RC oscillator frequency divided by 4.
PIC16F688 3.5.2.1 OSCTUNE Register The HFINTOSC is factory calibrated but can be adjusted in software by writing to the OSCTUNE register (Register 3-2). The default value of the OSCTUNE register is ‘0’. The value is a 5-bit two’s complement number. REGISTER 3-2: When the OSCTUNE register is modified, the HFINTOSC frequency will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred.
PIC16F688 3.5.3 LFINTOSC The Low-Frequency Internal Oscillator (LFINTOSC) is an uncalibrated 31 kHz internal clock source. The output of the LFINTOSC connects to a postscaler and multiplexer (see Figure 3-1). Select 31 kHz, via software, using the IRCF<2:0> bits of the OSCCON register. See Section 3.5.4 “Frequency Select Bits (IRCF)” for more information. The LFINTOSC is also the frequency for the Power-up Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM).
PIC16F688 FIGURE 3-6: INTERNAL OSCILLATOR SWITCH TIMING LF(1) HF HFINTOSC LFINTOSC (FSCM and WDT disabled) HFINTOSC Start-up Time 2-cycle Sync Running LFINTOSC ≠0 IRCF <2:0> =0 System Clock Note 1: When going from LF to HF.
PIC16F688 3.6 Clock Switching The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bit of the OSCCON register. 3.6.1 SYSTEM CLOCK SELECT (SCS) BIT The System Clock Select (SCS) bit of the OSCCON register selects the system clock source that is used for the CPU and peripherals.
PIC16F688 3.7.3 CHECKING TWO-SPEED CLOCK STATUS Checking the state of the OSTS bit of the OSCCON register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Word register (CONFIG), or the internal oscillator. FIGURE 3-7: TWO-SPEED START-UP HFINTOSC TOST OSC1 0 1 1022 1023 OSC2 Program Counter PC - N PC PC + 1 System Clock DS41203E-page 30 © 2009 Microchip Technology Inc.
PIC16F688 3.8 3.8.3 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator fail. The FSCM can detect oscillator failure any time after the Oscillator Start-up Timer (OST) has expired. The FSCM is enabled by setting the FCMEN bit in the Configuration Word register (CONFIG). The FSCM is applicable to all external oscillator modes (LP, XT, HS, EC, RC and RCIO).
PIC16F688 FIGURE 3-9: FSCM TIMING DIAGRAM Sample Clock Oscillator Failure System Clock Output Clock Monitor Output (Q) Failure Detected OSCFIF Test Note: Test Test The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity.
PIC16F688 4.0 I/O PORTS Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch. RA3 reads ‘0’ when MCLRE = 1. There are as many as twelve general purpose I/O pins available. Depending on which peripherals are enabled, some or all of the pins may not be available as general purpose I/O. In general, when a peripheral is enabled, the associated pin may not be used as a general purpose I/O pin. 4.
PIC16F688 4.2 4.2.3 Additional Pin Functions INTERRUPT-ON-CHANGE Every PORTA pin on the PIC16F688 has an interrupton-change option and a weak pull-up option. PORTA also provides an Ultra Low-Power Wake-up option. The next three sections describe these functions. Each of the PORTA pins is individually configurable as an interrupt-on-change pin. Control bits IOCAx enable or disable the interrupt function for each pin. Refer to Register 4-5. The interrupt-on-change is disabled on a Power-on Reset. 4.2.
PIC16F688 REGISTER 4-4: WPUA: WEAK PULL-UP PORTA REGISTER U-0 U-0 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1 — — WPUA5 WPUA4 — WPUA2 WPUA1 WPUA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 WPUA<5:4>: Weak Pull-up Control bits 1 = Pull-up enabled 0 = Pull-up disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 WPUA<2:0>: Weak Pull-up Control bits
PIC16F688 4.2.4 ULTRA LOW-POWER WAKE-UP The Ultra Low-Power Wake-up (ULPWU) on RA0 allows a slow falling voltage to generate an interrupton-change on RA0 without excess current consumption. The mode is selected by setting the ULPWUE bit of the PCON register. This enables a small current sink which can be used to discharge a capacitor on RA0. To use this feature, the RA0 pin is configured to output ‘1’ to charge the capacitor, interrupt-on-change for RA0 is enabled, and RA0 is configured as an input.
PIC16F688 4.2.5 PIN DESCRIPTIONS AND DIAGRAMS 4.2.5.1 Figure 4-1 shows the diagram for this pin. The RA0 pin is configurable to function as one of the following: Each PORTA pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the comparator or the A/D, refer to the appropriate section in this data sheet.
PIC16F688 4.2.5.2 RA1/AN1/C1IN-/VREF/ICSPCLK 4.2.5.3 RA2/AN2/T0CKI/INT/C1OUT Figure 4-2 shows the diagram for this pin. The RA1 pin is configurable to function as one of the following: Figure 4-3 shows the diagram for this pin.
PIC16F688 4.2.5.4 RA3/MCLR/VPP 4.2.5.5 RA4/AN3/T1G/OSC2/CLKOUT Figure 4-4 shows the diagram for this pin. The RA3 pin is configurable to function as one of the following: Figure 4-5 shows the diagram for this pin.
PIC16F688 4.2.5.6 RA5/T1CKI/OSC1/CLKIN FIGURE 4-6: BLOCK DIAGRAM OF RA5 Figure 4-6 shows the diagram for this pin.
PIC16F688 TABLE 4-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 7 ANSEL CMCON0 PCON INTCON IOCA OPTION_REG Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets 1111 1111 ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000 — — ULPWUE SBOREN — — POR BOR --01 --qq --0u --uu GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 000x 0000 000x — — IOCA5 IOCA4 IOCA3 IOC
PIC16F688 4.3 EXAMPLE 4-3: PORTC PORTC is a general purpose I/O port consisting of 6 bidirectional pins. The pins can be configured for either digital I/O or analog input to A/D converter or comparator. For specific information about individual functions such as the EUSART or the A/D converter, refer to the appropriate section in this data sheet. Note: The ANSEL and CMCON0 registers must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read ‘0’.
PIC16F688 4.3.1 RC0/AN4/C2IN+ 4.3.3 RC2/AN6 Figure 4-7 shows the diagram for this pin. The RC0 is configurable to function as one of the following: Figure 4-8 shows the diagram for this pin. The RC2 is configurable to function as one of the following: • a general purpose I/O • an analog input for the A/D Converter • an analog input to the comparator • a general purpose I/O • an analog input for the A/D Converter 4.3.2 Figure 4-8 shows the diagram for this pin.
PIC16F688 4.3.5 4.3.6 RC4/C2OUT/TX/CK RC5/RX/DT Figure 4-9 shows the diagram for this pin.
PIC16F688 5.0 TIMER0 MODULE 5.1 Timer0 Operation The Timer0 module is an 8-bit timer/counter with the following features: When used as a timer, the Timer0 module can be used as either an 8-bit timer or an 8-bit counter. • • • • • 5.1.
PIC16F688 5.1.3 SOFTWARE PROGRAMMABLE PRESCALER A single software programmable prescaler is available for use with either Timer0 or the Watchdog Timer (WDT), but not both simultaneously. The prescaler assignment is controlled by the PSA bit of the OPTION register. To assign the prescaler to Timer0, the PSA bit must be cleared to a ‘0’. There are 8 prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION register.
PIC16F688 REGISTER 5-1: OPTION_REG: OPTION REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 RAPU: PORTA Pull-up Enable bit 1 = PORTA pull-ups are disabled 0 = PORTA pull-ups are enabled by individual PORT latch values bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge
PIC16F688 6.0 TIMER1 MODULE WITH GATE CONTROL 6.1 The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter.
PIC16F688 6.2.1 INTERNAL CLOCK SOURCE When the internal clock source is selected the TMR1H:TMR1L register pair will increment on multiples of TCY as determined by the Timer1 prescaler. 6.2.2 EXTERNAL CLOCK SOURCE When the external clock source is selected, the Timer1 module may work as a timer or a counter. When counting, Timer1 is incremented on the rising edge of the external clock input T1CKI.
PIC16F688 6.7 Timer1 Interrupt The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set these bits: • Timer1 interrupt enable bit of the PIE1 register • PEIE bit of the INTCON register • GIE bit of the INTCON register The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine.
PIC16F688 6.9 Timer1 Control Register The Timer1 Control register (T1CON), shown in Register 6-1, is used to control Timer1 and select the various features of the Timer1 module.
PIC16F688 TABLE 6-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets 00-- --10 CMCON1 — — — — — — T1GSS C2SYNC ---- --10 INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 000x 0000 000x PIE1 EEIE ADIE RCIE C2IE C1IE OSFIE TXIE TMR1IE 0000 0000 0000 0000 EEIF ADIF RCIF C2IF C1IF OSFIF TXIF TMR1IF 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 0000
PIC16F688 7.0 COMPARATOR MODULE Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. The comparators are very useful mixed signal building blocks because they provide analog functionality independent of the program execution.
PIC16F688 FIGURE 7-2: COMPARATOR C1 OUTPUT BLOCK DIAGRAM MULTIPLEX Port Pins C1INV To C1OUT pin C1 D Q1 To Data Bus Q EN RD CMCON0 Set C1IF bit D Q3*RD CMCON0 Q EN CL Reset Note 1: 2: FIGURE 7-3: Q1 and Q3 are phases of the four-phase system clock (FOSC). Q1 is held high during Sleep mode.
PIC16F688 7.1.1 ANALOG INPUT CONNECTION CONSIDERATIONS A simplified circuit for an analog input is shown in Figure 7-4. Since the analog input pins share their connection with a digital input, they have reverse biased ESD protection diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur.
PIC16F688 7.2 Comparator Configuration There are eight modes of operation for the comparator. The CM<2:0> bits of the CMCON0 register are used to select these modes as shown in Figure 7-5.
PIC16F688 FIGURE 7-5: COMPARATOR I/O OPERATING MODES Comparators Reset (POR Default Value) CM<2:0> = 000 A VINC1INVIN+ C1IN+ A C2IN- C1 Off(1) C2 (1) Two Independent Comparators CM<2:0> = 100 VINC1IN- A C1IN+ VIN- A VIN+ C2IN+ A C2INOff C2IN+ Three Inputs Multiplexed to Two Comparators CM<2:0> = 001 C1INC1IN+ C2INC2IN+ A A VIN- CIS = 0 CIS = 1 VIN+ C1 C1OUT C2 C2OUT VIN- A VIN+ A C1INC1IN+ A A VIN- CIS = 0 CIS = 1 VIN+ C1 C1IN+ C2IN+ C2IN- C2IN+ A VIN- CIS = 0 CIS =
PIC16F688 7.3 Comparator Control The CMCON0 register (Register 7-1) provides access to the following comparator features: • • • • Mode selection Output state Output polarity Input switch 7.3.1 COMPARATOR OUTPUT STATE Each comparator state can always be read internally via the associated CxOUT bit of the CMCON0 register. The comparator outputs are directed to the CxOUT pins when CM<2:0> = 110.
PIC16F688 7.3.3 COMPARATOR INPUT SWITCH The inverting input of the comparators may be switched between two analog pins in the following modes: • CM<2:0> = 001 (Comparator C1 only) • CM<2:0> = 010 (Comparators C1 and C2) In the above modes, both pins remain in analog mode regardless of which pin is selected as the input. The CIS bit of the CMCON0 register controls the comparator input switch. 7.
PIC16F688 FIGURE 7-6: COMPARATOR INTERRUPT TIMING W/O CMCON0 READ Q1 Q3 CIN+ TRT COUT Set CMIF (level) CMIF reset by software FIGURE 7-7: COMPARATOR INTERRUPT TIMING WITH CMCON0 READ Q1 Q3 CIN+ 7.6 Operation During Sleep The comparator, if enabled before entering Sleep mode, remains active during Sleep. The additional current consumed by the comparator is shown separately in Section 14.0 “Electrical Specifications”.
PIC16F688 REGISTER 7-1: CMCON0: COMPARATOR CONFIGURATION REGISTER R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 C2OUT: Comparator 2 Output bit When C2INV = 0: 1 = C2 VIN+ > C2 VIN0 = C2 VIN+ < C2 VINWhen C2INV = 1: 1 = C2 VIN+ < C2 VIN0 = C2 VIN+ > C2 VIN- bit 6 C1OUT: Comparator 1 Output bit
PIC16F688 7.8 Comparator C2 Gating Timer1 7.9 This feature can be used to time the duration or interval of analog events. Clearing the T1GSS bit of the CMCON1 register will enable Timer1 to increment based on the output of Comparator C2. This requires that Timer1 is on and gating is enabled. See Section 6.0 “Timer1 Module with Gate Control” for details. It is recommended to synchronize Comparator C2 with Timer1 by setting the C2SYNC bit when the comparator is used as the Timer1 gate source.
PIC16F688 7.10 EQUATION 7-1: Comparator Voltage Reference The Comparator Voltage Reference module provides an internally generated voltage reference for the comparators.
PIC16F688 FIGURE 7-8: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM 16 Stages 8R R R R R VDD VRR 8R 16-1 Analog MUX VREN 15 14 CVREF to Comparator Input 2 1 0 VR<3:0>(1) VREN VR<3:0> = 0000 VRR Note 1: TABLE 7-2: Name ANSEL CMCON0 Care should be taken to ensure VREF remains within the comparator common mode input range. See Section 14.0 “Electrical Specifications” for more detail.
PIC16F688 8.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter.
PIC16F688 8.1 ADC Configuration When configuring and using the ADC the following functions must be considered: • • • • • • Port configuration Channel selection ADC voltage reference selection ADC conversion clock source Interrupt control Results formatting 8.1.1 For correct conversion, the appropriate TAD specification must be met. See A/D conversion requirements in Section 14.0 “Electrical Specifications” for more information. Table 8-1 gives examples of appropriate ADC clock selections.
PIC16F688 TABLE 8-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES (VDD > 3.0V) ADC Clock Period (TAD) ADC Clock Source Device Frequency (FOSC) ADCS<2:0> 20 MHz FOSC/2 000 100 ns FOSC/4 100 200 ns(2) 001 400 ns (2) 800 ns (2) FOSC/8 FOSC/16 101 FOSC/32 010 1.6 μs FOSC/64 110 3.2 μs FRC x11 2-6 μs(1,4) Legend: Note 1: 2: 3: 4: 8 MHz (2) 4 MHz 1 MHz (2) 2.0 μs 1.0 μs(2) 4.0 μs 2.0 μs 8.0 μs(3) 2.0 μs 4.0 μs 16.0 μs(3) 4.0 μs 8.0 μs(3) 32.0 μs(3) (3) 16.
PIC16F688 8.1.5 INTERRUPTS 8.1.6 The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital Conversion. The ADC interrupt flag is the ADIF bit in the PIR1 register. The ADC interrupt enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. Note: RESULT FORMATTING The 10-bit A/D Conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON0 register controls the output format.
PIC16F688 8.2 8.2.1 ADC Operation STARTING A CONVERSION To enable the ADC module, the ADON bit of the ADCON0 register must be set to a ‘1’. Setting the GO/ DONE bit of the ADCON0 register to a ‘1’ will start the Analog-to-Digital Conversion. Note: 8.2.2 The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section 8.2.5 “A/D Conversion Procedure”. 8.2.5 This is an example procedure for using the ADC to perform an Analog-to-Digital Conversion: 1. 2.
PIC16F688 EXAMPLE 8-1: A/D CONVERSION ;This code block configures the ADC ;for polling, Vdd reference, Frc clock ;and AN0 input. ; ;Conversion start & polling for completion ; are included.
PIC16F688 8.2.6 ADC REGISTER DEFINITIONS The following registers are used to control the operation of the ADC.
PIC16F688 REGISTER 8-3: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x ADRES9 ADRES8 ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown ADRES<9:2>: ADC Result Register bits Upper 8 bits of 10-bit conversion result REGISTER 8-4: ADRESL: ADC RESULT REGISTER LOW (ADRESL
PIC16F688 8.3 A/D Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 8-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure 8-4.
PIC16F688 FIGURE 8-4: ANALOG INPUT MODEL VDD ANx Rs CPIN 5 pF VA VT = 0.6V VT = 0.
PIC16F688 TABLE 8-2: SUMMARY OF ASSOCIATED ADC REGISTERS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets ADCON0 ADFM VCFG — CHS2 CHS1 CHS0 GO/DONE ADON 00-0 0000 00-0 0000 — ADCS2 ADCS1 ADCS0 — — — — -000 ---- -000 ---- ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111 ADCON1 ANSEL ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu ADRESL A/D Result Register Low Byte xxxx xxxx uuuu uuuu INTCO
PIC16F688 NOTES: DS41203E-page 76 © 2009 Microchip Technology Inc.
PIC16F688 9.0 DATA EEPROM AND FLASH PROGRAM MEMORY CONTROL Data EEPROM memory is readable and writable and the Flash program memory is readable during normal operation (full VDD range). These memories are not directly mapped in the register file space. Instead, they are indirectly addressed through the Special Function Registers.
PIC16F688 REGISTER 9-1: EEDAT: EEPROM DATA REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown EEDATn: Byte Value to Write to or Read from Data EEPROM bits REGISTER 9-2: EEADR: EEPROM ADDRESS REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PIC16F688 REGISTER 9-5: EECON1: EEPROM CONTROL REGISTER R/W-x U-0 U-0 U-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD — — — WRERR WREN WR RD bit 7 bit 0 Legend: S = Bit can only be set R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EEPGD: Program/Data EEPROM Select bit 1 = Accesses program memory 0 = Accesses data memory bit 6-4 Unimplemented: Read as ‘0’ bit 3 WRERR: EEPROM Error Flag bi
PIC16F688 9.1.2 READING THE DATA EEPROM MEMORY 9.1.3 WRITING TO THE DATA EEPROM MEMORY To read a data memory location, the user must write the address to the EEADR register, clear the EEPGD control bit of the EECON1 register, and then set control bit RD of the EECON1 register. The data is available in the very next cycle, in the EEDAT register; therefore, it can be read in the next instruction.
PIC16F688 9.1.4 READING THE FLASH PROGRAM MEMORY To read a program memory location, the user must write two bytes of the address to the EEADR and EEADRH registers, set the EEPGD control bit of the EECON1 register, and then set control bit RD of the EECON1 register. Once the read control bit is set, the program memory Flash controller will use the second instruction cycle to read the data. This causes the second instruction immediately following the “BSF EECON1,RD” instruction to be ignored.
PIC16F688 FIGURE 9-1: FLASH PROGRAM MEMORY READ CYCLE EXECUTION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC Flash ADDR Flash Data PC + 1 INSTR (PC) INSTR(PC - 1) executed here EEADRH,EEADR INSTR (PC + 1) BSF EECON1,RD executed here PC +3 PC+3 EEDATH,EEDAT INSTR(PC + 1) executed here PC + 5 PC + 4 INSTR (PC + 3) Forced NOP executed here INSTR (PC + 4) INSTR(PC + 3) executed here INSTR(PC + 4) executed here RD bit EEDATH EEDAT Register EERHLT TABLE 9-1:
PIC16F688 10.0 ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART) The EUSART module includes the following capabilities: • • • • • • • • • • The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is a serial I/O communications peripheral. It contains all the clock generators, shift registers and data buffers necessary to perform an input or output serial data transfer independent of device program execution.
PIC16F688 FIGURE 10-2: EUSART RECEIVE BLOCK DIAGRAM SPEN CREN RX/DT pin Baud Rate Generator Data Recovery FOSC BRG16 SPBRGH SPBRG Multiplier x4 x16 x64 SYNC 1 X 0 0 0 BRGH X 1 1 0 0 BRG16 X 1 0 1 0 Stop RCIDL RSR Register MSb Pin Buffer and Control +1 OERR (8) ••• 7 1 LSb 0 START RX9 ÷n n FERR RX9D RCREG Register FIFO 8 Data Bus RCIF RCIE Interrupt The operation of the EUSART module is controlled through three registers: • Transmit Status and Control (TXSTA) • Receiv
PIC16F688 10.1 EUSART Asynchronous Mode The EUSART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is implemented with two levels: a VOH mark state which represents a ‘1’ data bit, and a VOL space state which represents a ‘0’ data bit. NRZ refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission. An NRZ transmission port idles in the mark state.
PIC16F688 10.1.1.4 TSR Status 10.1.1.6 The TRMT bit of the TXSTA register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXREG. The TRMT bit remains clear until all bits have been shifted out of the TSR register. No interrupt logic is tied to this bit, so the user has to poll this bit to determine the TSR status. Note: 10.1.1.5 1. 2. 3.
PIC16F688 TABLE 10-1: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Name Bit 7 Bit 6 BAUDCTL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00 INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 000x 0000 000x PIE1 EEIE ADIE RCIE C2IE C1IE OSFIE TXIE TMR1IE 0000 0000 0000 0000 EEIF ADIF RCIF C2IF C1IF OSFIF TXIF TMR1IF 0000 0000 0000 0000 0000 0000 0000 0000
PIC16F688 10.1.2 EUSART ASYNCHRONOUS RECEIVER The Asynchronous mode would typically be used in RS-232 systems. The receiver block diagram is shown in Figure 10-2. The data is received on the RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate.
PIC16F688 10.1.2.4 Receive Framing Error Each character in the receive FIFO buffer has a corresponding framing error Status bit. A framing error indicates that a Stop bit was not seen at the expected time. The framing error status is accessed via the FERR bit of the RCSTA register. The FERR bit represents the status of the top unread character in the receive FIFO. Therefore, the FERR bit must be read before reading the RCREG.
PIC16F688 10.1.2.8 1. 2. 3. 4. 5. 6. 7. 8. 9. Asynchronous Reception Set-up: 10.1.2.9 Initialize the SPBRGH, SPBRG register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 10.3 “EUSART Baud Rate Generator (BRG)”). Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. If interrupts are desired, set the RCIE interrupt enable bit and set the GIE and PEIE bits of the INTCON register.
PIC16F688 TABLE 10-2: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Name Bit 7 Bit 6 BAUDCTL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00 INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 000x 0000 000x PIE1 EEIE ADIE RCIE C2IE C1IE OSFIE TXIE TMR1IE 0000 0000 0000 0000 EEIF ADIF RCIF C2IF C1IF OSFIF TXIF TMR1IF 0000 0000 0000 0000 0000 0000 0000 0000 PIR
PIC16F688 10.2 Clock Accuracy with Asynchronous Operation The factory calibrates the internal oscillator block output (INTOSC). However, the INTOSC frequency may drift as VDD or temperature changes, and this directly affects the asynchronous baud rate. Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind. REGISTER 10-1: The first (preferred) method uses the OSCTUNE register to adjust the INTOSC output.
PIC16F688 REGISTER 10-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset) bit 6 RX9:
PIC16F688 REGISTER 10-3: BAUDCTL: BAUD RATE CONTROL REGISTER R-0 R-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode: 1 = Auto-baud timer overflowed 0 = Auto-baud timer did not overflow Synchronous mode: Don’t care bit 6 RCIDL: Receiv
PIC16F688 10.3 EUSART Baud Rate Generator (BRG) The Baud Rate Generator (BRG) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous EUSART operation. By default, the BRG operates in 8-bit mode. Setting the BRG16 bit of the BAUDCTL register selects 16-bit mode. If the system clock is changed during an active receive operation, a receive error or data loss may result.
PIC16F688 TABLE 10-5: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE FOSC = 20.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 18.432 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 11.0592 MHz Actual Rate % Error FOSC = 8.000 MHz SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 300 — — — — — — — — — — — — 1200 1221 1.73 255 1200 0.00 239 1200 0.00 143 1202 0.16 103 2400 2404 0.16 129 2400 0.
PIC16F688 TABLE 10-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz Actual Rate % Error SPBRG value (decimal) 300 1200 — 1202 — 0.16 — 207 — 1200 — 0.00 — 191 — 1202 — 0.16 — 103 300 1202 0.16 0.16 207 51 2400 2404 0.16 103 2400 0.00 95 2404 0.16 51 2404 0.
PIC16F688 TABLE 10-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz FOSC = 8.000 MHz Actual Rate % Error SPBRG value (decimal) 300 1200 300.0 1200 0.00 -0.01 16665 4166 300.0 1200 0.00 0.00 15359 3839 300.0 1200 0.00 0.00 9215 2303 300.0 1200 0.00 -0.02 6666 1666 2400 2400 0.02 2082 2400 0.00 1919 2400 0.00 1151 2401 0.04 832 9600 9597 -0.
PIC16F688 10.3.1 AUTO-BAUD DETECT The EUSART module supports automatic detection and calibration of the baud rate. In the Auto-Baud Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RX signal, the RX signal is timing the BRG. The Baud Rate Generator is used to time the period of a received 55h (ASCII “U”) which is the Sync character for the LIN bus. The unique feature of this character is that it has five rising edges including the Stop bit edge.
PIC16F688 10.3.2 AUTO-BAUD OVERFLOW During the course of automatic baud detection, the ABDOVF bit of the BAUDCTL register will be set if the baud rate counter overflows before the fifth rising edge is detected on the RX pin. The ABDOVF bit indicates that the counter has exceeded the maximum count that can fit in the 16 bits of the SPBRGH:SPBRG register pair. After the ABDOVF has been set, the counter continues to count until the fifth rising edge is detected on the RX pin.
PIC16F688 FIGURE 10-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 OSC1 Auto Cleared Bit Set by User WUE bit RX/DT Line Note 1 RCIF Sleep Command Executed Note 1: 2: 10.3.4 If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is still active. This sequence should not depend on the presence of Q clocks.
PIC16F688 FIGURE 10-9: Write to TXREG SEND BREAK CHARACTER SEQUENCE Dummy Write BRG Output (Shift Clock) TX (pin) Start bit bit 0 bit 1 bit 11 Stop bit Break TXIF bit (Transmit interrupt Flag) TRMT bit (Transmit Shift Reg. Empty Flag) SENDB Sampled Here Auto Cleared SENDB (send Break control bit) DS41203E-page 102 © 2009 Microchip Technology Inc.
PIC16F688 10.4 EUSART Synchronous Mode Synchronous serial communications are typically used in systems with a single master and one or more slaves. The master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. There are two signal lines in Synchronous mode: a bidirectional data line and a clock line.
PIC16F688 FIGURE 10-10: SYNCHRONOUS TRANSMISSION RX/DT pin bit 0 bit 1 Word 1 bit 2 bit 7 bit 0 bit 1 Word 2 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to TXREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit TXEN bit ‘1’ Note: ‘1’ Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words.
PIC16F688 10.4.1.5 Synchronous Master Reception Data is received at the RX/DT pin. The RX/DT and TX/ CK pin output drivers are automatically disabled when the EUSART is configured for synchronous master receive operation. In Synchronous mode, reception is enabled by setting either the Single Receive Enable bit (SREN of the RCSTA register) or the Continuous Receive Enable bit (CREN of the RCSTA register).
PIC16F688 FIGURE 10-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RXREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
PIC16F688 10.4.2 SYNCHRONOUS SLAVE MODE The following bits are used to configure the EUSART for Synchronous slave operation: • • • • • SYNC = 1 CSRC = 0 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 1. 2. 3. 4. Setting the SYNC bit of the TXSTA register configures the device for synchronous operation. Clearing the CSRC bit of the TXSTA register configures the device as a slave.
PIC16F688 10.4.2.3 EUSART Synchronous Slave Reception 10.4.2.4 The operation of the Synchronous Master and Slave modes is identical (Section 10.4.1.5 “Synchronous Master Reception”), with the following exceptions: • Sleep • CREN bit is always set, therefore the receiver is never Idle • SREN bit, which is a “don’t care” in Slave mode A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep.
PIC16F688 11.0 SPECIAL FEATURES OF THE CPU The PIC16F688 has a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power-saving features and offer code protection.
PIC16F688 11.1 Configuration Bits The Configuration bits can be programmed (read as ‘0’), or left unprogrammed (read as ‘1’) to select various device configurations as shown in Register 11-1. These bits are mapped in program memory location 2007h. Note: Address 2007h is beyond the user program memory space. It belongs to the special configuration memory space (2000h-3FFFh), which can be accessed only during programming.
PIC16F688 REGISTER 11-1: Reserved CONFIG: CONFIGURATION WORD REGISTER Reserved Reserved Reserved FCMEN BOREN1(1) IESO BOREN0(1) bit 15 bit 8 CPD(2) CP(3) MCLRE(4) PWRTE WDTE FOSC2 FOSC1 FOSC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit P = Programmable’ U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Reserved: Reserved bits. Do Not Use.
PIC16F688 11.2 Reset The PIC16F688 differentiates between various kinds of Reset: a) b) c) d) e) f) Power-on Reset (POR) WDT Reset during normal operation WDT Reset during Sleep MCLR Reset during normal operation MCLR Reset during Sleep Brown-out Reset (BOR) Some registers are not affected in any Reset condition; their status is unknown on POR and unchanged in any other Reset.
PIC16F688 11.2.1 POWER-ON RESET FIGURE 11-2: The on-chip POR circuit holds the chip in Reset until VDD has reached a high enough level for proper operation. To take advantage of the POR, simply connect the MCLR pin through a resistor to VDD. This will eliminate external RC components usually needed to create Power-on Reset. A maximum rise time for VDD is required. See Section 14.0 “Electrical Specifications” for details. If the BOR is enabled, the maximum rise time specification does not apply.
PIC16F688 11.2.4 BROWN-OUT RESET (BOR) This will occur regardless of VDD slew rate. A Reset is not insured to occur if VDD falls below VBOD for less than parameter (TBOD). The BOREN0 and BOREN1 bits in the Configuration Word register selects one of four BOR modes. Two modes have been added to allow software or hardware control of the BOR enable. When BOREN<1:0> = 01, the SBOREN bit of the PCON register enables/disables the BOR, allowing it to be controlled in software.
PIC16F688 11.2.5 TIME-OUT SEQUENCE 11.2.6 On power-up, the time-out sequence is as follows: first, PWRT time-out is invoked after POR has expired, then OST is activated after the PWRT time-out has expired. The total time-out will vary based on oscillator configuration and PWRTE bit status. For example, in EC mode with PWRTE bit erased (PWRT disabled), there will be no time-out at all. Figure 11.2.1, Figure 11-5 and Figure 11-6 depict time-out sequences.
PIC16F688 FIGURE 11-4: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR) VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset FIGURE 11-5: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR) VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset FIGURE 11-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD) VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset DS41203E-page 116 © 2009 Microchip Technology Inc.
PIC16F688 TABLE 11-4: INITIALIZATION CONDITION FOR REGISTERS Address Power-on Reset MCLR Reset WDT Reset Brown-out Reset(1) Wake-up from Sleep through Interrupt Wake-up from Sleep through WDT Time-out — xxxx xxxx uuuu uuuu uuuu uuuu INDF 00h/80h/100h/180h xxxx xxxx uuuu uuuu uuuu uuuu TMR0 01h/101h xxxx xxxx uuuu uuuu uuuu uuuu PCL 02h/82h/102h/182h 0000 0000 0000 0000 PC + 1(3) STATUS 03h/83h/103h/183h 0001 1xxx 000q quuu(4) uuuq quuu(4) FSR 04h/84h/104h/184h xxxx xxxx uuuu
PIC16F688 TABLE 11-4: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED) Address Power-on Reset • MCLR Reset • WDT Reset • Brown-out Reset(1) OSCCON 8Fh -110 q000 -110 q000 -uuu uuuu OSCTUNE 90h ---0 0000 ---u uuuu ---u uuuu ANSEL 91h 1111 1111 1111 1111 uuuu uuuu WPUA 95h --11 -111 --11 -111 uuuu uuuu IOCA 96h --00 0000 --00 0000 --uu uuuu EEDATH 97h --00 0000 --00 0000 --uu uuuu EEADRH 98h ---- 0000 ---- 0000 ---- uuuu VRCON 99h 0-0- 0000 0-0- 0000 u-u- uuuu EED
PIC16F688 11.3 Interrupts The PIC16F688 has multiple sources of interrupt: • • • • • • • • • External Interrupt RA2/INT TMR0 Overflow Interrupt PORTA Change Interrupts 2 Comparator Interrupts A/D Interrupt Timer1 Overflow Interrupt EEPROM Data Write Interrupt Fail-Safe Clock Monitor Interrupt EUSART Receive and Transmit interrupts The Interrupt Control (INTCON) register and Peripheral Interrupt Request 1 (PIR1) register record individual interrupt requests in flag bits.
PIC16F688 11.3.1 RA2/INT INTERRUPT 11.3.2 External interrupt on RA2/INT pin is edge-triggered; either rising if the INTEDG bit of the OPTION register is set, or falling if the INTEDG bit is clear. When a valid edge appears on the RA2/INT pin, the INTF bit of the INTCON register is set. This interrupt can be disabled by clearing the INTE control bit of the INTCON register. The INTF bit must be cleared in software in the Interrupt Service Routine before re-enabling this interrupt.
PIC16F688 FIGURE 11-8: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT (3) (4) INT pin (1) (1) INTF Flag (INTCON<1>) Interrupt Latency (2) (5) GIE bit (INTCON<7>) Instruction Flow PC PC Instruction Fetched Inst (PC) Instruction Executed Inst (PC - 1) Note 1: 2: 3: 4: 5: 0004h PC + 1 PC + 1 — Inst (PC + 1) Dummy Cycle Inst (PC) 0005h Inst (0004h) Inst (0005h) Dummy Cycle Inst (0004h) INTF flag is sampled here (ever
PIC16F688 11.4 Context Saving During Interrupts During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt (e.g., W and Status registers). This must be implemented in software. Since the lower 16 bytes of all banks are common in the PIC16F688 (see Figure 2-2), temporary holding registers, W_TEMP and STATUS_TEMP, should be placed in here.
PIC16F688 11.5 Watchdog Timer (WDT) The WDT has the following features: • • • • • Operates from the LFINTOSC (31 kHz) Contains a 16-bit prescaler Shares an 8-bit prescaler with Timer0 Time-out period is from 1 ms to 268 seconds Configuration bit and software controlled WDT is cleared under certain conditions described in Table 11-7. 11.5.1 WDT OSCILLATOR The WDT derives its time base from the 31 kHz LFINTOSC. The LTS bit does not reflect that the LFINTOSC is enabled.
PIC16F688 REGISTER 11-2: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 U-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4-1 WDTPS<3:0>: Watchdog Timer Period Select bits Bit Value = Prescale Rate 0000 = 1:32 0001 = 1:64 0010 = 1:128 0011 = 1:256 0100 = 1:512 (Reset value
PIC16F688 11.6 Power-Down Mode (Sleep) The Power-down mode is entered by executing a SLEEP instruction. If the Watchdog Timer is enabled: • • • • • WDT will be cleared but keeps running. PD bit in the Status register is cleared. TO bit is set. Oscillator driver is turned off. I/O ports maintain the status they had before SLEEP was executed (driving high, low or high-impedance).
PIC16F688 FIGURE 11-10: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(2) CLKOUT(4) INT pin INTF flag (INTCON<1>) Interrupt Latency (3) GIE bit (INTCON<7>) Processor in Sleep Instruction Flow PC Instruction Fetched Instruction Executed Note 11.
PIC16F688 11.9 In-Circuit Serial Programming This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. The device is placed into a Program/Verify mode by holding the RA0 and RA1 pins low, while raising the MCLR (VPP) pin from VIL to VIHH. See the “PIC12F6XX/16F6XX Memory Programming Specification” (DS41204) for more information.
PIC16F688 NOTES: DS41203E-page 128 © 2009 Microchip Technology Inc.
PIC16F688 12.0 INSTRUCTION SET SUMMARY The PIC16F688 instruction set is highly orthogonal and is comprised of three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations Each PIC16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction.
PIC16F688 TABLE 12-2: PIC16F684 INSTRUCTION SET Mnemonic, Operands 14-Bit Opcode Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f – f, d f, d f, d f, d f, d f, d f, d f – f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move
PIC16F688 12.2 Instruction Descriptions ADDLW Add literal and W Syntax: [ label ] ADDLW Operands: 0 ≤ k ≤ 255 Operation: (W) + k → (W) Status Affected: C, DC, Z Description: The contents of the W register are added to the eight-bit literal ‘k’ and the result is placed in the W register. k BCF Bit Clear f Syntax: [ label ] BCF Operands: 0 ≤ f ≤ 127 0≤b≤7 Operation: 0 → (f) Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared.
PIC16F688 BTFSS Bit Test f, Skip if Set CLRWDT Clear Watchdog Timer Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRWDT Operands: 0 ≤ f ≤ 127 0≤b<7 Operands: None Operation: 00h → WDT 0 → WDT prescaler, 1 → TO 1 → PD Status Affected: TO, PD Description: CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set.
PIC16F688 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) - 1 → (destination); skip if result = 0 Operation: (f) + 1 → (destination), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in the W register.
PIC16F688 MOVF Move f Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] MOVF f,d MOVWF Move W to f Syntax: [ label ] MOVWF Operands: 0 ≤ f ≤ 127 Operation: (W) → (f) f Operation: (f) → (dest) Status Affected: None Status Affected: Z Description: Description: The contents of register f is moved to a destination dependent upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself.
PIC16F688 RETFIE Return from Interrupt RETLW Return with literal in W Syntax: [ label ] Syntax: [ label ] Operands: None Operands: 0 ≤ k ≤ 255 Operation: TOS → PC, 1 → GIE Operation: k → (W); TOS → PC Status Affected: None Status Affected: None Description: Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction.
PIC16F688 RLF Rotate Left f through Carry SLEEP Enter Sleep mode Syntax: [ label ] Syntax: [ label ] SLEEP Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: None Operation: Operation: See description below Status Affected: C Description: The contents of register ‘f’ are rotated one bit to the left through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’.
PIC16F688 SUBWF Subtract W from f XORLW Exclusive OR literal with W Syntax: [ label ] SUBWF f,d Syntax: [ label ] XORLW k Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ k ≤ 255 (f) - (W) → (destination) Operation: (W) .XOR. k → (W) Operation: Status Affected: C, DC, Z Description: SWAPF Status Affected: Z Description: The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register.
PIC16F688 NOTES: DS41203E-page 138 © 2009 Microchip Technology Inc.
PIC16F688 13.
PIC16F688 13.2 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging.
PIC16F688 13.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment.
PIC16F688 13.11 PICSTART Plus Development Programmer 13.13 Demonstration, Development and Evaluation Boards The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins.
PIC16F688 14.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings(†) Ambient temperature under bias..........................................................................................................-40° to +125°C Storage temperature ........................................................................................................................ -65°C to +150°C Voltage on VDD with respect to VSS ..................................................................................................
PIC16F688 FIGURE 14-1: PIC16F688 VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C 5.5 5.0 VDD (V) 4.5 4.0 3.5 3.0 2.5 2.0 0 8 10 20 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE FIGURE 14-2: 125 ± 5% Temperature (°C) 85 ± 2% 60 ± 1% 25 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS41203E-page 144 © 2009 Microchip Technology Inc.
PIC16F688 14.1 DC Characteristics: PIC16F688 -I (Industrial) PIC16F688 -E (Extended) DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No. Min Typ† Max Units Sym Characteristic Conditions VDD Supply Voltage 2.0 2.0 3.0 4.5 — — — — 5.5 5.5 5.5 5.5 V V V V FOSC < = 8 MHz: HFINTOSC, EC FOSC < = 4 MHz FOSC < = 10 MHz FOSC < = 20 MHz D002* VDR RAM Data Retention Voltage(1) 1.
PIC16F688 14.2 DC Characteristics: PIC16F688 -I (Industrial) PIC16F688 -E (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended DC CHARACTERISTICS Param No. D010 Conditions Device Characteristics Min Typ† Max Units VDD Supply Current (IDD) D011* D012 D013* D014 D015 D016* D017 D018 D019 (1, 2) — 16 23 μA 2.0 — 27 38 μA 3.0 — 47 75 μA 5.0 — 180 250 μA 2.
PIC16F688 14.3 DC Characteristics: PIC16F688-I (Industrial) DC CHARACTERISTICS Param No. D020 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Conditions Device Characteristics Power-down Base Current(IPD)(2) D021 Min Typ† Max Units VDD Note WDT, BOR, Comparators, VREF and T1OSC disabled — 0.05 1.2 μA 2.0 — 0.15 1.5 μA 3.0 — 0.35 1.8 μA 5.0 — 150 500 nA 3.0 -40°C ≤ TA ≤ +25°C — 1.0 2.2 μA 2.
PIC16F688 14.4 DC Characteristics: PIC16F688-E (Extended) DC CHARACTERISTICS Param No. D020E Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C for extended Conditions Device Characteristics Power-down Base Current (IPD)(2) D021E Min — Typ† 0.05 Max 9 Units μA VDD Note 2.0 WDT, BOR, Comparators, VREF and T1OSC disabled — 0.15 11 μA 3.0 — 0.35 15 μA 5.0 — 1 28 μA 2.0 — 2 30 μA 3.0 — 3 35 μA 5.0 D022E — 42 65 μA 3.
PIC16F688 14.5 DC Characteristics: PIC16F688 -I (Industrial) PIC16F688 -E (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended DC CHARACTERISTICS Param No. Sym VIL Characteristic Min Typ† Max Units Vss Vss Conditions — 0.8 V 4.5V ≤ VDD ≤ 5.5V — 0.15 VDD V 2.0V ≤ VDD ≤ 4.5V Vss — 0.2 VDD V 2.0V ≤ VDD ≤ 5.
PIC16F688 14.5 DC Characteristics: PIC16F688 -I (Industrial) PIC16F688 -E (Extended) (Continued) DC CHARACTERISTICS Param No.
PIC16F688 14.6 Thermal Considerations Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Param No. TH01 TH02 TH03 TH04 TH05 TH06 TH07 Note 1: 2: 3: Sym θJA Characteristic Thermal Resistance Junction to Ambient Typ Units 69.8 85.0 100.4 46.3 32.5 31.0 31.7 2.6 150 — — C/W C/W C/W C/W C/W C/W C/W C/W C W W Conditions 14-pin PDIP package 14-pin SOIC package 14-pin TSSOP package 16-pin QFN 4x0.
PIC16F688 14.7 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2.
PIC16F688 14.8 AC Characteristics: PIC16F688 (Industrial, Extended) FIGURE 14-4: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1/CLKIN OS02 OS04 OS04 OS03 OSC2/CLKOUT (LP, XT, HS Modes) OSC2/CLKOUT (CLKOUT Mode) TABLE 14-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Param No.
PIC16F688 TABLE 14-2: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No. Sym Characteristic Freq Tolerance Min Typ† Max Units Conditions OS06 TWARM Internal Oscillator Switch when running(3) — — — 2 TOSC Slowest clock OS07 TSC Fail-Safe Sample Clock Period(1) — — 21 — ms LFINTOSC/64 OS08 HFOSC Internal Calibrated HFINTOSC Frequency(2) ±1% 7.92 8.0 8.08 MHz VDD = 3.5V, 25°C ±2% 7.84 8.0 8.
PIC16F688 FIGURE 14-5: CLKOUT AND I/O TIMING Cycle Write Fetch Read Execute Q4 Q1 Q2 Q3 FOSC OS12 OS11 OS20 OS21 CLKOUT OS19 OS18 OS16 OS13 OS17 I/O pin (Input) OS14 OS15 I/O pin (Output) New Value Old Value OS18, OS19 TABLE 14-3: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No. Sym Characteristic Min Typ† Max Units Conditions TOSH2CKL FOSC↑ to CLKOUT↓ (1) — — 70 ns VDD = 5.
PIC16F688 FIGURE 14-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Start-Up Time Internal Reset(1) Watchdog Timer Reset(1) 31 34 34 I/O pins Note 1: Asserted low.
PIC16F688 TABLE 14-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No.
PIC16F688 FIGURE 14-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 49 47 TMR0 or TMR1 TABLE 14-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No.
PIC16F688 TABLE 14-6: COMPARATOR SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No. Sym Characteristics CM01 VOS Input Offset Voltage CM02 VCM Input Common Mode Voltage CM03* CMRR Common Mode Rejection Ratio CM04* TRT Response Time Min Typ† Max Units — ± 5.0 ± 10 mV 0 — VDD – 1.
PIC16F688 TABLE 14-8: PIC16F688 A/D CONVERTER (ADC) CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Param Sym No. Characteristic Min Typ† Max Units Conditions AD01 NR Resolution — — 10 bits AD02 EIL Integral Error — — ±1 LSb VREF = 5.12V AD03 EDL Differential Error — — ±1 LSb No missing codes to 10 bits VREF = 5.12V AD04 EOFF Offset Error — — ±1 LSb VREF = 5.12V AD07 EGN LSb VREF = 5.
PIC16F688 TABLE 14-9: PIC16F688 A/D CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Param No. Sym AD130* TAD Characteristic A/D Clock Period A/D Internal RC Oscillator Period AD131 TCNV Conversion Time (not including Acquisition Time)(1) Min Typ† 1.6 — 9.0 μs TOSC-based, VREF ≥ 3.0V 3.0 — 9.0 μs TOSC-based, VREF full range 3.0 6.0 9.0 μs ADCS<1:0> = 11 (ADRC mode) At VDD = 2.5V 1.6 4.0 6.0 μs At VDD = 5.
PIC16F688 FIGURE 14-9: PIC16F688 A/D CONVERSION TIMING (NORMAL MODE) BSF ADCON0, GO AD134 1 TCY (TOSC/2(1)) AD131 Q4 AD130 A/D CLK 9 A/D Data 8 7 6 3 2 1 0 NEW_DATA OLD_DATA ADRES 1 TCY ADIF GO DONE Note 1: Sampling Stopped AD132 Sample If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
PIC16F688 15.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range.
PIC16F688 FIGURE 15-2: MAXIMUM IDD vs. FOSC OVER VDD (EC MODE) EC Mode 4.0 3.5 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 5.5V 5.0V 3.0 IDD (mA) 2.5 4.0V 2.0 3.0V 1.5 2.0V 1.0 0.5 0.0 1 MHz 2 MHz 4 MHz 6 MHz 8 MHz 10 MHz 12 MHz 14 MHz 16 MHz 18 MHz 20 MHz FOSC FIGURE 15-3: TYPICAL IDD vs. FOSC OVER VDD (HS MODE) 4.0 3.5 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) Temp)+ 5.5V 5,0V 3.0 4.
PIC16F688 FIGURE 15-4: MAXIMUM IDD vs. FOSC OVER VDD (HS MODE) 5.0 4.5 Typical: Typical: Statistical Statistical Mean Mean @25°C @25×C Maximum: Maximum: Mean Mean (Worst-case (Worst CaseTemp) + 3σ (-40°C Temp)+to 3 125°C) 4.0 5.5V 5.0V IDD (mA) 3.5 4.5V 3.0 2.5 2.0 4.0V 3.5V 3.0V 1.5 1.0 0.5 0.0 4 MHz 10 MHz 16 MHz 20 MHz FOSC TYPICAL IDD vs.
PIC16F688 FIGURE 15-6: MAXIMUM IDD vs. VDD OVER FOSC (XT MODE) 1,800 1,600 1,400 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) IDD (uA) 1,200 1,000 4 MHz 800 600 400 1 MHz 200 0 2 2.5 3 3.5 4 4.5 5 5.5 VDD (V) FIGURE 15-7: TYPICAL IDD vs.
PIC16F688 FIGURE 15-8: MAXIMUM IDD vs. VDD (EXTRC MODE) 2,000 Typical: Statistical Mean @25°C Maximum: Maximum:Mean Mean(Worst-case (Worst CaseTemp) Temp)+ +3s3 (-40×Ctoto125°C) 125×C) (-40°C 1,800 1,600 1,400 4 MHz IDD (uA) 1,200 1,000 800 1 MHz 600 400 200 0 2 2.5 3 3.5 4 4.5 5 5.5 VDD (V) FIGURE 15-9: IDD vs.
PIC16F688 FIGURE 15-10: IDD vs. VDD (LP MODE) 90 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 80 70 IDD (uA) 60 32 kHz Maximum 50 40 30 32 kHz Typical 20 10 0 2 2.5 3 3.5 4 4.5 5 5.5 VDD (V) FIGURE 15-11: TYPICAL IDD vs. FOSC OVER VDD (HFINTOSC MODE) HFINTOSC 1,800 1,600 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 5.5V 5.0V 1,400 1,200 IDD (uA) 4.0V 1,000 3.0V 800 600 2.
PIC16F688 FIGURE 15-12: MAXIMUM IDD vs. FOSC OVER VDD (HFINTOSC MODE) 2,500 2,000 Typical: Statistical Mean @ 25°C Maximum: Mean (Worst-case Temp) +3σ (-40°C to 125°C) 5.5V 5.0V IDD (uA) 1,500 4.0V 3.0V 1,000 2.0V 500 0 125 kHz 250 kHz 500 kHz 1 MHz 2 MHz 4 MHz 8 MHz VDD (V) FIGURE 15-13: TYPICAL IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) Typical (Sleep Mode all Peripherals Disabled) 0.45 0.
PIC16F688 FIGURE 15-14: MAXIMUM IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) Maximum (Sleep Mode all Peripherals Disabled) 18.0 16.0 Typical: Statistical Mean @25°C Maximum: Mean + 3σ Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 14.0 Max. 125°C IPD (μA) 12.0 10.0 8.0 6.0 4.0 Max. 85°C 2.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 15-15: COMPARATOR IPD vs.
PIC16F688 FIGURE 15-16: BOR IPD vs. VDD OVER TEMPERATURE 160 140 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 120 IPD (μA) 100 Maximum 80 Typical 60 40 20 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 15-17: TYPICAL WDT IPD vs. VDD (25°C) 3.0 2.5 IPD (uA) 2.0 1.5 1.0 0.5 0.0 2.0V 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V 5.5V VDD (V) © 2009 Microchip Technology Inc.
PIC16F688 FIGURE 15-18: MAXIMUM WDT IPD vs. VDD OVER TEMPERATURE 40.0 35.0 Max. 125°C 30.0 IPD (uA) 25.0 20.0 15.0 10.0 Max. 85°C 5.0 0.0 2.0V 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V 4.5 5.0 5.5V VDD (V) FIGURE 15-19: WDT PERIOD vs. VDD OVER TEMPERATURE 30 28 Typical: Statistical Mean @25°C Maximum: Mean + 3σ (-40°C to 125°C) Maximum: Mean + 3σ Max. (125°C) 26 Max. (85°C) 24 Time (ms) 22 20 Typical 18 16 14 Minimum 12 10 2.0 2.5 3.0 3.5 4.0 5.5 VDD (V) © 2009 Microchip Technology Inc.
PIC16F688 FIGURE 15-20: WDT PERIOD vs. TEMPERATURE Vdd = 5V 30 28 Typical: Statistical Mean @25°C Maximum: Mean + 3σ 26 Maximum 24 Time (ms) 22 20 Typical 18 16 Minimum 14 12 10 -40°C 25°C 85°C 125°C Temperature (°C) FIGURE 15-21: CVREF IPD vs. VDD OVER TEMPERATURE (HIGH RANGE) High Range 140 120 Typical: Statistical Mean @25°C Maximum: Mean + 3σ (-40°C to 125°C) 100 IPD (μA) Max. 125°C 80 Max. 85°C 60 Typical 40 20 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PIC16F688 FIGURE 15-22: CVREF IPD vs. VDD OVER TEMPERATURE (LOW RANGE) 180 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 160 140 120 IPD (μA) Max. 125°C 100 Max. 85°C 80 Typical 60 40 20 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 15-23: VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V) (VDD = 3V, -40×C TO 125×C) 0.8 0.7 Typical: Statistical Mean @25°C Maximum: Mean + 3σ Max. 125°C 0.6 VOL (V) 0.5 Max. 85°C 0.4 Typical 25°C 0.3 0.2 Min. -40°C 0.
PIC16F688 FIGURE 15-24: VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V) 0.45 Typical: Statistical Mean @25°C Typical: Statistical Maximum: Mean + 3σ Mean Maximum: Means + 3 0.40 Max. 125°C 0.35 Max. 85°C VOL (V) 0.30 0.25 Typ. 25°C 0.20 0.15 Min. -40°C 0.10 0.05 0.00 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 IOL (mA) FIGURE 15-25: VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V) 3.5 3.0 Max. -40°C Typ. 25°C 2.5 Min. 125°C VOH (V) 2.0 1.5 1.
PIC16F688 FIGURE 15-26: VOH vs. IOH OVER TEMPERATURE (VDD = 5.0V) ( , ) 5.5 5.0 Max. -40°C Typ. 25°C VOH (V) 4.5 Min. 125°C 4.0 3.5 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 3.0 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 -5.0 IOH (mA) FIGURE 15-27: TTL INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE (TTL Input, -40×C TO 125×C) 1.7 1.5 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) Max.
PIC16F688 FIGURE 15-28: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE (ST Input, -40×C TO 125×C) 4.0 VIH Max. 125°C 3.5 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) VIH Min. -40°C VIN (V) 3.0 2.5 2.0 VIL Max. -40°C 1.5 VIL Min. 125°C 1.0 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 15-29: T1OSC IPD vs. VDD OVER TEMPERATURE (32 kHz) 45.0 40.
PIC16F688 FIGURE 15-30: COMPARATOR RESPONSE TIME (RISING EDGE) 531 806 1000 900 Max. 125°C Response Time (nS) 800 700 600 Note: 500 VCM = VDD - 1.5V)/2 V+ input = VCM V- input = Transition from VCM + 100MV to VCM - 20MV Max. 85°C 400 300 Typ. 25°C 200 Min. -40°C 100 0 2.0 2.5 4.0 5.5 VDD (V) FIGURE 15-31: COMPARATOR RESPONSE TIME (FALLING EDGE) 1000 900 Max. 125°C 800 Response Time (nS) 700 600 500 Note: VCM = VDD - 1.
PIC16F688 FIGURE 15-32: LFINTOSC FREQUENCY vs. VDD OVER TEMPERATURE (31 kHz) LFINTOSC 31Khz 45,000 40,000 Max. -40°C 35,000 Typ. 25°C Frequency (Hz) 30,000 25,000 20,000 Min. 85°C Min. 125°C 15,000 10,000 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 5,000 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 15-33: ADC CLOCK PERIOD vs.
PIC16F688 FIGURE 15-34: TYPICAL HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE 16 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 14 85°C 12 25°C Time (μs) 10 -40°C 8 6 4 2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 15-35: MAXIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE -40C to +85C 25 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) Time (μs) 20 15 85°C 25°C 10 -40°C 5 0 2.0 2.5 3.0 3.
PIC16F688 FIGURE 15-36: MINIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE -40C to +85C 10 9 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 8 7 Time (μs) 85°C 6 25°C 5 -40°C 4 3 2 1 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 15-37: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (25°C) 5 4 Change from Calibration (%) 3 2 1 0 -1 -2 -3 -4 -5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) © 2009 Microchip Technology Inc.
PIC16F688 FIGURE 15-38: TYPICAL HFINTOSC FREQUENCY CHANGE OVER DEVICE VDD (85°C) 5 4 Change from Calibration (%) 3 2 1 0 -1 -2 -3 -4 -5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 15-39: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (125°C) 5 4 Change from Calibration (%) 3 2 1 0 -1 -2 -3 -4 -5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) © 2009 Microchip Technology Inc.
PIC16F688 FIGURE 15-40: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (-40°C) 5 4 Change from Calibration (%) 3 2 1 0 -1 -2 -3 -4 -5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) © 2009 Microchip Technology Inc.
PIC16F688 NOTES: © 2009 Microchip Technology Inc.
PIC16F688 16.0 PACKAGING INFORMATION 16.1 Package Marking Information 14-Lead PDIP (Skinny DIP) XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN 14-Lead SOIC (3.90 mm) XXXXXXXXXXX XXXXXXXXXXX YYWWNNN 14-Lead TSSOP XXXXXXXX YYWW NNN 16-Lead QFN Legend: XX...
PIC16F688 16.2 Package Details The following sections give the technical details of the packages.
PIC16F688 14-Lead Plastic Small Outline (SL) – Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 3 e h b α h A A2 c φ L A1 β L1 Units Dimension Limits Number of Pins MILLMETERS MIN N NOM MAX 14 Pitch e Overall Height A – 1.27 BSC – Molded Package Thickness A2 1.25 – – Standoff § A1 0.10 – 0.
PIC16F688 3 % & % ! % 4 " ) ' % 4 $ % % " % %% 255))) & &5 4 DS41203E-page 188 © 2009 Microchip Technology Inc.
PIC16F688 14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 e b c φ A2 A A1 Units Dimension Limits Number of Pins L L1 MILLIMETERS MIN N NOM MAX 14 Pitch e Overall Height A – 0.65 BSC – Molded Package Thickness A2 0.80 1.00 1.05 Standoff A1 0.05 – 0.15 1.
PIC16F688 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41203E-page 190 © 2009 Microchip Technology Inc.
PIC16F688 16-Lead Plastic Quad Flat, No Lead Package (ML) – 4x4x0.9 mm Body [QFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D2 D EXPOSED PAD e E2 E 2 2 1 1 b TOP VIEW K N N NOTE 1 L BOTTOM VIEW A3 A A1 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 16 Pitch e Overall Height A 0.80 0.65 BSC 0.90 1.00 Standoff A1 0.00 0.02 0.05 Contact Thickness A3 0.
PIC16F688 3 % & % ! % 4 " ) ' % 4 $ % % " % %% 255))) & &5 4 DS41203E-page 192 © 2009 Microchip Technology Inc.
PIC16F688 APPENDIX A: DATA SHEET REVISION HISTORY Revision A APPENDIX B: MIGRATING FROM OTHER PIC® DEVICES This is a new data sheet. This discusses some of the issues in migrating from other PIC devices to the PIC16F6XX family of devices. Revision B B.1 Rewrites of the Oscillator and Special Features of the CPU Sections. General corrections to Figures and formatting. TABLE B-1: Revision C Revised Electrical Section and added Char Data. Added Golden Chapters.
PIC16F688 NOTES: DS41203E-page 194 © 2009 Microchip Technology Inc.
PIC16F688 INDEX A A/D Specifications.................................................... 160, 161 Absolute Maximum Ratings .............................................. 143 AC Characteristics Industrial and Extended ............................................ 153 Load Conditions ........................................................ 152 ADC .................................................................................... 65 Acquisition Requirements ...........................................
PIC16F688 Specifications ............................................................ 159 CONFIG Register.............................................................. 111 Configuration Bits.............................................................. 110 CPU Features ................................................................... 109 Customer Change Notification Service ............................. 199 Customer Notification Service........................................... 199 Customer Support .....
PIC16F688 ADC ............................................................................ 69 Associated Registers ................................................ 121 Comparator ................................................................. 59 Context Saving.......................................................... 122 Interrupt-on-Change.................................................... 34 PORTA Interrupt-on-Change .................................... 120 RA2/INT .....................................
PIC16F688 RCSTA (Receive Status and Control)......................... 93 Reset Values............................................................. 117 Reset Values (Special Registers) ............................. 118 Special Function Register Map ..................................... 8 Special Register Summary ........................................... 9 STATUS ...................................................................... 13 T1CON ..................................................................
PIC16F688 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PIC16F688 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PIC16F688 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Device Temperature Range Package Pattern Examples: a) b) Device PIC16F688, PIC16F688T(1) VDD range 2.0V to 5.5V Temperature Range I E Package ML P SL ST Pattern QTP, SQTPSM or ROM Code; Special Requirements (blank otherwise) = -40°C to +85°C = -40°C to +125°C PIC16F688-E/P 301 = Extended Temp.
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