Datasheet

© 2008 Microchip Technology Inc. DS41262E-page 119
PIC16F631/677/685/687/689/690
10.0 DATA EEPROM AND FLASH
PROGRAM MEMORY
CONTROL
Data EEPROM memory is readable and writable and
the Flash program memory (PIC16F685/PIC16F689/
PIC16F690 only) is readable during normal operation
(full V
DD range). These memories are not directly
mapped in the register file space. Instead, they are indi-
rectly addressed through the Special Function Regis-
ters (SFRs). There are six SFRs used to access these
memories:
• EECON1
• EECON2
• EEDAT
• EEDATH (PIC16F685/PIC16F689/PIC16F690 only)
• EEADR
• EEADRH (PIC16F685/PIC16F689/PIC16F690 only)
When interfacing the data memory block, EEDAT holds
the 8-bit data for read/write, and EEADR holds the
address of the EEDAT location being accessed. These
devices, except for the PIC16F631, have 256 bytes of
data EEPROM with an address range from 0h to 0FFh.
The PIC16F631 has 128 bytes of data EEPROM with
an address range from 0h to 07Fh.
When accessing the program memory block of the
PIC16F685/PIC16F689/PIC16F690 devices, the EEDAT
and EEDATH registers form a 2-byte word that holds the
14-bit data for read/write, and the EEADR and EEADRH
registers form a 2-byte word that holds the 12-bit address
of the EEPROM location being read. These devices
(PIC16F685/PIC16F689/PIC16F690) have 4K words of
program EEPROM with an address range from 0h to
0FFFh. The program memory allows one-word reads.
The EEPROM data memory allows byte read and write.
A byte write automatically erases the location and
writes the new data (erase before write).
The write time is controlled by an on-chip timer. The
write/erase voltages are generated by an on-chip
charge pump rated to operate over the voltage range of
the device for byte or word operations.
When the device is code-protected, the CPU may
continue to read and write the data EEPROM memory
and read the program memory. When code-protected,
the device programmer can no longer access data or
program memory.
10.1 EEADR and EEADRH Registers
The EEADR and EEADRH registers can address up to
a maximum of 256 bytes of data EEPROM or up to a
maximum of 4K words of program EEPROM.
When selecting a program address value, the MSB of
the address is written to the EEADRH register and the
LSB is written to the EEADR register. When selecting a
data address value, only the LSB of the address is
written to the EEADR register.
10.1.1 EECON1 AND EECON2 REGISTERS
EECON1 is the control register for EE memory
accesses.
Control bit EEPGD (PIC16F685/PIC16F689/PIC16F690)
determines if the access will be a program or data mem-
ory access. When clear, as it is when reset, any subse-
quent operations will operate on the data memory. When
set, any subsequent operations will operate on the pro-
gram memory. Program memory can only be read.
Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set, in
software. They are cleared in hardware at completion
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental, premature
termination of a write operation.
The WREN bit, when set, will allow a write operation to
data EEPROM. On power-up, the WREN bit is clear.
The WRERR bit is set when a write operation is
interrupted by a MCLR
or a WDT Time-out Reset
during normal operation. In these situations, following
Reset, the user can check the WRERR bit and rewrite
the location.
Interrupt flag bit EEIF of the PIR2 register is set when
write is complete. It must be cleared in the software.
EECON2 is not a physical register. Reading EECON2
will read all ‘0’s. The EECON2 register is used
exclusively in the data EEPROM write sequence.