Datasheet

PIC16F684

FIGURE 3-9: FSCM TIMING DIAGRAM

TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

OSCFIF

System

Clock

Output

Sample Clock

Failure

Detected

Oscillator

Failure

Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in

this example have been chosen for clarity.

(Q)

Tes t

Test Test

Clock Monitor Output

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR, BOR

Value on

all other

Resets

(1)

CONFIG

(2)

CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 — —

OSCCON

— IRCF2 IRCF1 IRCF0 OSTS HTS LTS SCS -110 x000 -110 x000

OSCTUNE

— — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 ---u uuuu

PIE1

EEIE ADIE CCP1IE C2IE C1IE OSFIE TMR2IE TMR1IE 0000 0000 0000 0000

PIR1

EEIF ADIF CCP1IF C2IF C1IF OSFIF TMR2IF TMR1IF 0000 0000 0000 0000

Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators.

Note 1: Other (non Power-up) Resets include MCLR

Reset and Watchdog Timer Reset during normal operation.

2: See Configuration Word register (Register 12-1) for operation of all register bits.