Datasheet

© 2007 Microchip Technology Inc. DS41202F-page 9
PIC16F684
TABLE 2-1: PIC16F684 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Page
Bank 0
00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 19, 104
01h TMR0 Timer0 Module’s Register xxxx xxxx 43, 104
02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 19, 104
03h STATUS IRP
(1)
RP1
(1)
RP0 TO PD ZDCC0001 1xxx 13, 104
04h FSR Indirect Data Memory Address Pointer xxxx xxxx 19, 104
05h PORTA
(2)
— — RA5 RA4 RA3 RA2 RA1 RA0 --x0 x000 31, 104
06h — Unimplemented — —
07h PORTC
(2)
— — RC5 RC4 RC3 RC2 RC1 RC0 --xx 0000 40, 104
08h — Unimplemented — —
09h — Unimplemented — —
0Ah PCLATH
— — — Write Buffer for upper 5 bits of Program Counter ---0 0000 19, 104
0Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 15, 104
0Ch PIR1
EEIF ADIF CCP1IF C2IF C1IF OSFIF TMR2IF TMR1IF 0000 0000 17, 104
0Dh — Unimplemented — —
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx 47, 104
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx 47, 104
10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR1CS TMR1ON 0000 0000 50, 104
11h TMR2 Timer2 Module Register 0000 0000 53, 104
12h T2CON
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 54, 104
13h CCPR1L Capture/Compare/PWM Register 1 Low Byte XXXX XXXX 80, 104
14h CCPR1H Capture/Compare/PWM Register 1 High Byte XXXX XXXX 80, 104
15h CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 79, 104
16h PWM1CON PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 96, 104
17h ECCPAS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 93, 104
18h WDTCON
— — —
WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 111, 104
19h CMCON0 C2OUT C1OUT
C2INV C1INV CIS CM2 CM1 CM0 0000 0000 61, 104
1Ah CMCON1
— — — — — — T1GSS C2SYNC ---- --10 62, 104
1Bh — Unimplemented — —
1Ch — Unimplemented — —
1Dh — Unimplemented — —
1Eh ADRESH Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result xxxx xxxx 71, 104
1Fh ADCON0 ADFM VCFG
— CHS2 CHS1 CHS0 GO/DONE ADON 00-0 0000 70, 104
Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: IRP and RP1 bits are reserved, always maintain these bits clear.
2: Port pins with analog functions controlled by the ANSEL register will read ‘0’ immediately after a Reset even though the data latches are
either undefined (POR) or unchanged (other Resets).