Datasheet

PIC16F630/676
DS40039E-page 58 © 2007 Microchip Technology Inc.
9.3.1 MCLR
PIC16F630/676 devices have a noise filter in the
MCLR
Reset path. The filter will detect and ignore
small pulses.
It should be noted that a WDT Reset does not drive
MCLR
pin low.
The behavior of the ESD protection on the MCLR
pin
has been altered from previous devices of this family.
Voltages applied to the pin that exceed its specification
can result in both MCLR
Resets and excessive current
beyond the device specification during the ESD event.
For this reason, Microchip recommends that the MCLR
pin no longer be tied directly to VDD. The use of an RC
network, as shown in Figure 9-5, is suggested.
An internal MCLR
option is enabled by setting the
MCLRE bit in the configuration word. When enabled,
MCLR is internally tied to VDD. No internal pull-up
option is available for the MCLR
pin.
FIGURE 9-5: RECOMMENDED MCLR
CIRCUIT
9.3.2 POWER-ON RESET (POR)
The on-chip POR circuit holds the chip in RESET until
V
DD has reached a high enough level for proper
operation. To take advantage of the POR, simply tie the
MCLR pin through a resistor to VDD. This will eliminate
external RC components usually needed to create
Power-on Reset. A maximum rise time for VDD is
required. See Electrical Specifications for details (see
Section 12.0). If the BOD is enabled, the maximum rise
time specification does not apply. The BOD circuitry will
keep the device in RESET until V
DD reaches VBOD (see
Section 9.3.5).
When the device starts normal operation (exits the
RESET condition), device operating parameters (i.e.,
voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in RESET until the operating
conditions are met.
For additional information, refer to Application Note
AN607 “Power-up Trouble Shooting”.
9.3.3 POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 72 ms (nominal)
time-out on power-up only, from POR or Brown-out
Detect. The Power-up Timer operates on an internal
RC oscillator. The chip is kept in RESET as long as
PWRT is active. The PWRT delay allows the V
DD to
rise to an acceptable level. A configuration bit, PWRTE
can disable (if set) or enable (if cleared or
programmed) the Power-up Timer. The Power-up
Timer should always be enabled when Brown-out
Detect is enabled.
The Power-up Time delay will vary from chip to chip
and due to:
•V
DD variation
• Temperature variation
• Process variation.
See DC parameters for details (Section 12.0).
9.3.4 OSCILLATOR START-UP TIMER
(OST)
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal
oscillator or resonator has started and stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
Note: The POR circuit does not produce an inter-
nal RESET when V
DD declines.
VDD
PIC16F630/676
MCLR
R1
1 kΩ (or greater)
C1
0.1
μf
(optional, not critical)