Datasheet

© 2007 Microchip Technology Inc. DS40039E-page 23
PIC16F630/676
3.2.3.3 RA2/AN2/T0CKI/INT/COUT
Figure 3-2 shows the diagram for this pin. The RA2 pin
is configurable to function as one of the following:
• a general purpose I/O
• an analog input for the A/D (PIC16F676 only)
• a digital output from the comparator
• the clock input for TMR0
• an external edge triggered interrupt
FIGURE 3-2: BLOCK DIAGRAM OF RA2
3.2.3.4 RA3/MCLR
/VPP
Figure 3-3 shows the diagram for this pin. The RA3 pin
is configurable to function as one of the following:
• a general purpose input
• as Master Clear Reset
FIGURE 3-3: BLOCK DIAGRAM OF RA3
I/O pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
VDD
D
EN
Q
D
EN
Q
Weak
Analog
Input Mode
Data Bus
WR
WPUA
RD
WPUA
RD
PORTA
WR
PORTA
WR
TRISA
RD
TRISA
WR
IOCA
RD
IOCA
Interrupt-on-Change
To A/D Converter
0
1
COUT
COUT
Enable
To INT
To TMR0
Analog
Input Mode
RAPU
RD PORTA
Analog
Input
Mode
I/O pin
V
SS
D
Q
CK
Q
D
EN
Q
Data Bus
RD PORTA
RD
PORTA
WR
IOCA
RD
IOCA
Interrupt-on-Change
RESET
MCLRE
RD
TRISA
VSS
D
EN
Q
MCLRE