Datasheet

PIC16F627A/628A/648A
DS40044F-page 32 © 2007 Microchip Technology Inc.
FIGURE 5-2: BLOCK DIAGRAM OF
RA2/AN2/V
REF PIN
FIGURE 5-3: BLOCK DIAGRAM OF THE RA3/AN3/CMP1 PIN
Data
Bus
QD
Q
CK
WR
PORTA
WR
TRISA
Data Latch
TRIS Latch
RD
RD PORTA
Analog
RA2 P
in
QD
Q
CK
Input Mode
DQ
EN
To Comparator
Schmitt Trigger
Input Buffer
VROE
V
REF
VDD
VSS
TRISA
(CMCON Reg.)
Data
Bus
QD
Q
CK
WR
PORTA
WR
TRISA
Data Latch
TRIS Latch
RD
RD PORTA
Analog
RA3 Pin
QD
Q
CK
DQ
EN
To Comparator
Schmitt Trigger
Input Buffer
Input Mode
Comparator Output
Comparator Mode = 110
VDD
VSS
TRISA
(CMCON Reg.)
(CMCON Reg.)
1
0