Datasheet

PIC12F635/PIC16F636/639
DS41232D-page 84 © 2007 Microchip Technology Inc.
FIGURE 7-10: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
REGISTER 7-5: VRCON: VOLTAGE REFERENCE CONTROL REGISTER
R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
VREN —VRR— VR3 VR2 VR1 VR0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 VREN: CV
REF Enable bit
1 = CV
REF circuit powered on
0 = CV
REF circuit powered down, no IDD drain and CVREF = VSS.
bit 6 Unimplemented: Read as ‘0’
bit 5 VRR: CVREF Range Selection bit
1 = Low range
0 = High range
bit 4 Unimplemented: Read as ‘0’
bit 3-0 VR<3:0>: CV
REF Value Selection bits (0 ≤ VR<3:0> ≤ 15)
When V
RR = 1: CVREF = (VR<3:0>/24) * VDD
When VRR = 0: CVREF = VDD/4 + (VR<3:0>/32) * VDD
VRR
8R
VR<3:0>
(1)
16-1 Analog
8R R R R R
CVREF to
16 Stages
Comparator
Input
VREN
VDD
MUX
VR<3:0> = 0000
VREN
VRR
0
1
2
14
15
Note 1: Care should be taken to ensure VREF remains
within the comparator common mode input
range. See Section 15.0 “Electrical Specifica-
tions” for more detail.