Datasheet
© 2007 Microchip Technology Inc. DS41232D-page 55
PIC12F635/PIC16F636/639
4.2.4.5 RA4/T1G/OSC2/CLKOUT
Figure 4-5 shows the diagram for this pin. The RA4 pin
is configurable to function as one of the following:
• a general purpose I/O
• a Timer1 gate input
• a crystal/resonator connection
• a clock output
FIGURE 4-5: BLOCK DIAGRAM OF RA4
4.2.4.6 RA5/T1CKI/OSC1/CLKIN
Figure 4-6 shows the diagram for this pin. The RA5 pin
is configurable to function as one of the following:
• a general purpose I/O
• a Timer1 clock input
• a crystal/resonator connection
• a clock input
FIGURE 4-6: BLOCK DIAGRAM OF RA5
I/O pi
n
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
EN
Q
D
EN
Q
XTAL
RD
PORTA
WR
PORTA
WR
TRISA
RD
TRISA
WR
IOCA
RD
IOCA
FOSC/4
Oscillator
Circuit
OSC1
CLKOUT
0
1
CLKOUT
Enable
Enable
RD PORTA
T1G To Timer1
INTOSC/
RC/EC
(2)
CLKOUT
Enable
Note 1: Oscillator modes are XT, HS, LP, LPTMR1 and
CLKOUT Enable.
2: With CLKOUT option.
Interrupt-on-
change
D
Q
CK
Q
Data Bus
WR
WPUDA
RD
WPUDA
RAPU
D
Q
CK
Q
WR
WDA
RD
WDA
VDD
Weak
Weak
VSS
CLK
(1)
Modes
Q1
I/O pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
EN
Q
D
EN
Q
RD
PORTA
WR
PORTA
WR
TRISA
RD
TRISA
WR
IOCA
RD
IOCA
T1G To Timer1
INTOSC
Mode
RD PORTA
OSC2
(2)
Note 1: Oscillator modes are XT, HS, LP and LPTMR1.
2: When using Timer1 with LP oscillator, the
Schmitt Trigger is bypassed.
Interrupt-on-
change
Oscillator
Circuit
D
Q
CK
Q
Data Bus
WR
WPUDA
RD
WPUDA
RAPU
D
Q
CK
Q
WR
WDA
RD
WDA
VDD
Weak
Weak
VSS
CLK
(1)
Modes
Q1