Datasheet
© 2007 Microchip Technology Inc. DS41232D-page 53
PIC12F635/PIC16F636/639
4.2.4.2 RA1/C1IN-/VREF/ICSPCLK
Figure 4-2 shows the diagram for this pin. The RA1 pin
is configurable to function as one of the following:
• a general purpose I/O
• an analog input to the comparator
• In-Circuit Serial Programming™ clock
FIGURE 4-2: BLOCK DIAGRAM OF RA1
4.2.4.3 RA2/T0CKI/INT/C1OUT
Figure 4-3 shows the diagram for this pin. The RA2 pin
is configurable to function as one of the following:
• a general purpose I/O
• the clock input for Timer0
• an external edge-triggered interrupt
• a digital output from the comparator
FIGURE 4-3: BLOCK DIAGRAM OF RA2
I/O pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
EN
Q
D
EN
Q
Data Bus
WR
WPUDA
RD
WPUDA
RD PORTA
RD
PORTA
WR
PORTA
WR
TRISA
RD
TRISA
WR
IOCA
RD
IOCA
Interrupt-on-
To Comparator
RAPU
Analog
Input Mode
(1)
change
D
Q
CK
Q
WR
WDA
RD
WDA
VDD
Weak
Weak
VSS
Analog
Input Mode
(1)
Q1
Note 1: Comparator mode determines Analog Input mode.
I/O pin
VDD
VSS
D
Q
CK
Q
D
Q
CK
Q
D
Q
CK
Q
D
EN
Q
D
EN
Q
RD
PORTA
WR
PORTA
WR
TRISA
RD
TRISA
WR
IOCA
RD
IOCA
0
1
C1OUT
To INT
To Timer0
RD PORTA
Interrupt-on-
change
D
Q
CK
Q
Data Bus
WR
WPUDA
RD
WPUDA
RAPU
D
Q
CK
Q
WR
WDA
RD
WDA
VDD
Weak
Weak
VSS
C1OUT
Enable
Q1