Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller SSOP 20 8-Bit 20 MHz I/O number 11

PIC12F635/PIC16F636/639

TABLE 2-4: PIC16F636/639 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR/BOR/

WUR

Page

Bank 1

80h INDF Addressing this location uses contents of FSR to address data memory

(not a physical register)

xxxx xxxx

32,137

81h OPTION_REG RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111

63,137

82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000

32,137

83h STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx

26,137

84h FSR Indirect Data Memory Address Pointer xxxx xxxx

32,137

85h TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111

86h — Unimplemented — —

87h TRISC

— — TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111

88h — Unimplemented — —

89h — Unimplemented — —

8Ah PCLATH

— — — Write Buffer for upper 5 bits of Program Counter ---0 0000

32,137

8Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF

(3)

0000 000x

28,137

8Ch PIE1 EEIE LVDIE CRIE C2IE C1IE OSFIE —TMR1IE0000 00-0

29,137

8Dh — Unimplemented — —

8Eh PCON

— — ULPWUE SBOREN WUR —PORBOR --01 q-qq --0u u-uu

8Fh OSCCON

— IRCF2 IRCF1 IRCF0 OSTS HTS LTS SCS -110 q000 -110 x000

90h OSCTUNE

— — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 ---u uuuu

91h — Unimplemented — —

92h — Unimplemented — —

93h — Unimplemented — —

94h LVDCON

— —IRVSTLVDEN— LVDL2 LVDL1 LVDL0 --00 -000 --00 -000

95h WPUDA

(2)

— — WPUDA5 WPUDA4 — WPUDA2 WPUDA1 WPUDA0 --11 -111 --11 -111

96h IOCA

— — IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 --00 0000 --00 0000

97h WDA

(2)

— — WDA5 WDA4 — WDA2 WDA1 WDA0 --11 -111 --11 -111

9Bh — Unimplemented — —

99h VRCON VREN

—VRR— VR3 VR2 VR1 VR0 0-0- 0000 0-0- 0000

9Ah EEDAT EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000

9Bh EEADR EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000

9Ch EECON1

— — — — WRERR WREN WR RD ---- x000 ---- q000

9Dh EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- ---- ----

9Eh — Unimplemented — —

9Fh — Unimplemented — —

Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,

shaded = unimplemented

Note 1: Other (non Power-up) Resets include MCLR

Reset and Watchdog Timer Reset during normal operation.

2: RA3 pull-up is enabled when pin is configured as MCLR

in the Configuration Word register.

3: MCLR

and WDT Reset do not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set

again if the mismatch exists.