Datasheet

© 2007 Microchip Technology Inc. DS41232D-page 141
PIC12F635/PIC16F636/639
FIGURE 12-8: INT PIN INTERRUPT TIMING
TABLE 12-6: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR, BOR
Value on
all other
Resets
INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 000x 0000 000x
IOCA — — IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 --00 0000 --00 0000
PIR1 EEIF LVDIF CRIF C2IF
(1)
C1IF OSFIF —TMR1IF0000 00-0 0000 00-0
PIE1 EEIE LVDIE CRIE C2IE
(1)
C1IE OSFIE —TMR1IE0000 00-0 0000 00-0
Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’, q = value depends upon condition.
Shaded cells are not used by the Interrupt module.
Note 1: PIC16F636/639 only.
Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4
OSC1
CLKOUT
(3)
INT pin
INTF Flag
(INTCON<1>)
GIE bit
(INTCON<7>)
Instruction Flow
PC
Instruction
Fetched
Instruction
Executed
Interrupt Latency
(2)
PC
PC + 1
PC + 1
0004h
0005h
Inst (0004h)
Inst (0005h)
Dummy Cycle
Inst (PC)
Inst (PC + 1)
Inst (PC – 1)
Inst (0004h)
Dummy Cycle
Inst (PC)
—
Note 1: INTF flag is sampled here (every Q1).
2: Asynchronous interrupt latency = 3-4 T
CY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency
is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available only in INTOSC and RC Oscillator modes.
4: For minimum width of INT pulse, refer to AC specifications in Section 15.0 “Electrical Specifications”.
5: INTF is enabled to be set any time during the Q4-Q1 cycles.
(1)
(4)
(5)
(1)