Datasheet

PIC12F635/PIC16F636/639
DS41232D-page 132 © 2007 Microchip Technology Inc.
12.3 Power-on Reset
The on-chip POR circuit holds the chip in Reset until VDD
has reached a high enough level for proper operation. To
take advantage of the POR, simply connect the MCLR
pin through a resistor to VDD. This will eliminate external
RC components usually needed to create Power-on
Reset. A maximum rise time for V
DD is required. See
Section 15.0 “Electrical Specifications” for details. If
the BOR is enabled, the maximum rise time specification
does not apply. The BOR circuitry will keep the device in
Reset until VDD reaches VBOD (see Section 12.6
“Brown-out Reset (BOR)”).
When the device starts normal operation (exits the
Reset condition), device operating parameters (i.e.,
voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
For additional information, refer to the Application Note
AN607, “Power-up Trouble Shooting” (DS00607).
12.4 Wake-up Reset (WUR)
The PIC12F635/PIC16F636/639 has a modified
wake-up from Sleep mechanism. When waking from
Sleep, the WUR function resets the device and
releases Reset when V
DD reaches an acceptable level.
If the WURE
bit is enabled (‘0’) in the Configuration
Word register, the device will Wake-up Reset from
Sleep through one of the following events:
1. On any event that causes a wake-up event. The
peripheral must be enabled to generate an
interrupt or wake-up, GIE state is ignored.
2. When WURE is enabled, RA3 will always
generate an interrupt-on-change signal during
Sleep.
The WUR
, POR and BOR bits in the PCON register
and the TO
and PD bits in the STATUS register can be
used to determine the cause of device Reset.
To allow WUR upon RA3 change:
1. Enable the WUR function, WURE
Configuration
Bit = 0.
2. Enable RA3 as an input, MCLRE Configuration
Bit = 0.
3. Read PORTA to establish the current state of
RA3.
4. Execute SLEEP instruction.
5. When RA3 changes state, the device will
wake-up and then reset. The WUR
bit in PCON
will be cleared to ‘0’.
12.4.1 POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 64 ms (nominal)
time-out on power-up only, from POR or Brown-out
Reset. The Power-up Timer operates from the 31 kHz
LFINTOSC oscillator. For more information, see
Section 3.5 “Internal Clock Modes”. The chip is kept
in Reset as long as PWRT is active. The PWRT delay
allows the V
DD to rise to an acceptable level. A
Configuration bit, PWRTE
, can disable (if set) or enable
(if cleared or programmed) the Power-up Timer. The
Power-up Timer should be enabled when Brown-out
Reset is enabled, although it is not required.
The Power-up Timer delay will vary from chip-to-chip
due to:
•V
DD variation
• Temperature variation
• Process variation
See DC parameters for details (Section 15.0
“Electrical Specifications”).
12.5 MCLR
PIC12F635/PIC16F636/639 has a noise filter in the
MCLR
Reset path. The filter will ignore small pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low. See Figure 12-2 for the recommended
MCLR
circuit.
An internal MCLR
option is enabled by clearing the
MCLRE bit in the Configuration Word register. When
cleared, MCLR is internally tied to VDD and an internal
weak pull-up is enabled for the MCLR
pin. In-Circuit
Serial Programming is not affected by selecting the
internal MCLR option.
Note: The POR circuit does not produce an
internal Reset when V
DD declines. To
re-enable the POR, V
DD must reach VSS
for a minimum of 100 μs.
Note: Voltage spikes below VSS at the MCLR
pin, inducing currents greater than 80 mA,
may cause latch-up. Thus, a series resis-
tor of 50-100
Ω should be used when
applying a “low” level to the MCLR
pin,
rather than pulling this pin directly to V
SS.