Datasheet

PIC12F635/PIC16F636/639
DS41232D-page 120 © 2007 Microchip Technology Inc.
FIGURE 11-18: SPI READ SEQUENCE
CS
LFDATA/RSSI/
CCLK/SDIO
Driven low by MCU
T SU T HD
T SCCS
T HI T LO
1/F SCLK
T CS 1
T
CSH
T CS 0
SDI
(input)
SCLK
(input)
ALERT
(output)
LFDATA
(output)
MCU pin to Input
MCU pin to Input
Driven low by MCU
MCU pin to Output
16 Clocks for Read Command,
T
CSSC
T CSSC
T CS 1
T
CSH
T CS 0
SDO
SCLK
(input)
ALERT
(output)
LFDATA
(output)
MCU pin to Input
Driven low by MCU
16 Clocks for Read Result
(output)
SCLK/ALERT
ALERT
LFDATA
(output)
(output)
Driven low by MCU
MCU pin still Input
1
2
3
4
5
6
7
8
9
10
T DO
MSb LSb
T
CSSC
Address and Dummy Data
MCU SPI Read Details:
1. Drive the AFE’s open collector ALERT
output low.
• To ensure no false clocks occur when CS
drops.
2. Drop CS
• AFE SCLK/ALERT becomes SCLK input.
• LFDATA/RSSI/CCLK/SDIO becomes SDI input.
3. Change LFDATA/RSSI/CCLK/SDIO connected pin to output.
• Driving SPI data.
4. Clock in 16-bit SPI Read sequence.
• Command, address and dummy data.
5. Change LFDATA/RSSI/CCLK/SDIO connected pin to input.
6. Raise CS
to complete the SPI Read entry of command and address.
7. Drop CS.
• AFE SCLK/ALERT becomes SCLK input.
• LFDATA/RSSI/CCLK/SDIO becomes SDO output.
8. Clock out 16-bit SPI Read result.
• First seven bits clocked-out are dummy bits.
• Next eight bits are the Configuration register data.
• The last bit is the Configuration register row parity bit.
9. Raise CS
to complete the SPI Read.
10. Change SCLK/ALERT
back to input.
Note: The T
CSH is considered as one clock. Therefore, the
Configuration register data appears at 6th clock after T
CSH.