Datasheet

© 2007 Microchip Technology Inc. DS41232D-page 101
PIC12F635/PIC16F636/639
FIGURE 11-2: LC INPUT PATH
A
A
RF
Limiter
MOD
FET
Capacitor
Tuning
Var
Atten
FGA1 FGA2
Full-Wave
LFDATA
X Y
Z
LCX/ LCY/ LCZ
LCCOM
Carrier
>4VPP
WAKEZ
WAKEY
CLKDIV
DATOUT
AGC Feedback
Peak
REF GEN
0.1V
X Y
Z
B
AGCACT
AGCSIG
Demodulator
Decode
AGC
Registers
Configuration
Sens.
Control
Legend: FGA = Fixed Gain Amplifier FWR = Full-wave Rectifier LPF = Low-pass Filter PD = Peak Detector
00
Detector
+
–
+
–
+
–
0.4V
≈
Data Slicer
MOD Depth Control
Output Enable
Filter
10
Amplifier
≈
Rectifier
Low-Pass
Filter
Detector
Auto Channel
Selector
32 kHz
Clock/AGC
/1 OR /4
C
CHX CHY
CHZ
ACT
AUTOCHSEL
LFDATA
01 10 11
RSSI GEN
C
Timer
÷ 64
RSSI
DETZ
DETY
DETX
WAKEX