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PIC12F635/PIC16F636/639

Data Sheet

8/14-Pin, Flash-Based 8-Bit

CMOS Microcontrollers

with nanoWatt Technology

*8-bit, 8-pin Devices Protected by Microchip’s Low Pin Count Patent: U. S. Patent No. 5,847,450. Additional U.S. and

foreign patents and applications may be issued or pending.

Summary of content (234 pages)

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PIC12F635/PIC16F636/639 Data Sheet 8/14-Pin, Flash-Based 8-Bit CMOS Microcontrollers with nanoWatt Technology *8-bit, 8-pin Devices Protected by Microchip’s Low Pin Count Patent: U. S. Patent No. 5,847,450. Additional U.S. and foreign patents and applications may be issued or pending. © 2007 Microchip Technology Inc.
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Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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PIC12F635/PIC16F636/639 8/14-Pin Flash-Based, 8-Bit CMOS Microcontrollers With nanoWatt Technology High-Performance RISC CPU: Peripheral Features: • Only 35 instructions to learn: - All single-cycle instructions except branches • Operating speed: - DC – 20 MHz oscillator/clock input - DC – 200 ns instruction cycle • Interrupt capability • 8-level deep hardware stack • Direct, Indirect and Relative Addressing modes • 6/12 I/O pins with individual direction control: - High-current source/sink for direct LE
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PIC12F635/PIC16F636/639 Program Memory Data Memory Device Flash (words) SRAM (bytes) EEPROM (bytes) I/O Comparators Low Frequency Analog Front-End PIC12F635 1024 64 128 6 1 N PIC16F636 2048 128 256 12 2 N PIC16F639 2048 128 256 12 2 Y Note 1: Any references to PORTA, RAn, TRISA and TRISAn refer to GPIO, GPn, TRISIO and TRISIOn, respectively. 2: VDDT is the supply voltage of the Analog Front-End section (PIC16F639 only).
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PIC12F635/PIC16F636/639 8-Pin Diagrams (PDIP, SOIC, DFN, DFN-S) VDD 1 GP5/T1CKI/OSC1/CLKIN 2 GP4/T1G/OSC2/CLKOUT 3 GP3/MCLR/VPP 4 PIC12F635 PDIP, SOIC 8 VSS 7 GP0/C1IN+/ICSPDAT/ULPWU 6 GP1/C1IN-/ICSPCLK 5 GP2/T0CKI/INT/C1OUT DFN, DFN-S GP3/MCLR/VDD GP0 3 4 8 7 6 5 VSS GP0/CIN+/ICSPDAT/ULPWU GP1/CIN-/ICSPCLK GP2/T0CKI/INT/COUT 8-PIN SUMMARY (PDIP, SOIC, DFN, DFN-S) TABLE 1: I/O 1 2 PIC12F635 VDD GP5/T1CKI/OSC1/CLKIN GP4/T1G/OSC2/CLKOUT Pin Comparators Timer Interrupts Pull-up
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PIC12F635/PIC16F636/639 VDD RA5/T1CKI/OSC1/CLKIN RA4/T1G/OSC2/CLKOUT RA3/MCLR/VPP RC5 RC4/C2OUT RC3 TABLE 2: I/O 1 2 3 4 5 6 7 PIC16F636 14-Pin Diagram (PDIP, SOIC, TSSOP) 14 13 12 11 10 9 8 VSS RA0/C1IN+/ICSPDAT/ULPWU RA1/C1IN-/VREF/ICSPCLK RA2/T0CKI/INT/C1OUT RC0/C2IN+ RC1/C2INRC2 14-PIN SUMMARY (PDIP, SOIC, TSSOP) Pin Comparators Timer Interrupts Pull-ups Basic RA0 13 C1IN+ — IOC Y ICSPDAT/ULPWU RA1 12 C1IN- — IOC Y VREF/ICSPCLK RA2 11 C1OUT T0CKI INT/IOC Y — MCLR/VPP R
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PIC12F635/PIC16F636/639 16-Pin Diagram RC5 RA0 NC NC VSS 15 14 13 2 PIC16F636 11 10 3 RA3/MCLR/VPP I/O 12 1 RA4/AN3/T1G/OSC2/CLKOUT TABLE 3: VDD RA5/T1CKI/OSC1/CLKIN 16 QFN 9 7 8 RC1/C2IN- 6 RC3 RC2 5 RC4/C2OUT 4 RA0/C1IN+/ICSPDAT/ULPWU RA1/C1IN-/VREF/ICSPCLK RA2/T0CKI/INT/C1OUT RC0/C2IN+ 16-PIN SUMMARY Pin Comparators Timer Interrupts Pull-ups Basic 12 C1IN+ — IOC Y ICSPDAT/ULPWU RA1 11 C1IN- — IOC Y VREF/ICSPCLK RA2 10 C1OUT T0CKI INT/IOC Y — — IOC Y(2
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PIC12F635/PIC16F636/639 20-Pin Diagram 1 2 3 4 5 6 7 8 9 10 VDD RA5/T1CKI/OSC1/CLKIN RA4/T1G/OSC2/CLKOUT RA3/MCLR/VPP RC5 RC4/C2OUT RC3/LFDATA/RSSI/CCLK/SDIO VDDT(3) LCZ LCY TABLE 4: PIC16F639 SSOP 20 19 18 17 16 15 14 13 12 11 VSS RA0/C1IN+/ICSPDAT/ULPWU RA1/C1IN-/VREF/ICSPCLK RA2/TOCKI/INT/C1OUT RC0/C2IN+ RC1/C2IN-/CS RC2/SCLK/ALERT VSST(4) LCCOM LCX 20-PIN SUMMARY I/O Pin Analog Front-End Comparators Timer Interrupts Pull-ups Basic RA0 19 — C1IN+ — IOC Y ICSPDAT/ULPWU RA1 18 —
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PIC12F635/PIC16F636/639 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 Memory Organization ................................................................................................................................................................. 17 3.0 Clock Sources ......................................................................
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PIC12F635/PIC16F636/639 1.0 DEVICE OVERVIEW Block Diagrams and pinout descriptions of the devices are as follows: This document contains device specific information for the PIC12F635/PIC16F636/639 devices.
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PIC12F635/PIC16F636/639 FIGURE 1-2: PIC16F636 BLOCK DIAGRAM Configuration 13 Flash 2K x 14 Program Memory Program Bus 8 Data Bus Program Counter PORTA RA0 RA1 RAM 128 bytes File Registers 8-level Stack (13-bit) 14 RAM Addr RA2 RA3 RA4 RA5 9 Addr MUX Instruction Reg Direct Addr 7 Indirect Addr 8 FSR Reg PORTC RC0 RC1 RC2 STATUS Reg 8 RC3 RC4 RC5 Instruction Decode and Control OSC1/CLKIN Timing Generation OSC2/CLKOUT 8 MHz Internal Oscillator 31 kHz Internal Oscillator Power-up Timer O
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PIC12F635/PIC16F636/639 FIGURE 1-3: PIC16F639 BLOCK DIAGRAM Configuration 13 Flash 2K x 14 Program Memory Program Bus 8 Data Bus Program Counter PORTA RA0 RA1 8-level Stack (13-bit) 14 RA2 RAM 128 bytes File Registers RAM Addr (1) RA3 RA4 RA5 9 Addr MUX Instruction Reg PORTC Direct Addr 7 Indirect Addr 8 RC0 RC1 FSR Reg RC2 RC3 STATUS Reg 8 RC4 RC5 Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset Programmable Low-voltage Detect Wake-up Reset Inst
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PIC12F635/PIC16F636/639 TABLE 1-1: PIC12F635 PINOUT DESCRIPTIONS Name GP0/C1IN+/ICSPDAT/ULPWU GP1/C1IN-/ICSPCLK GP2/T0CKI/INT/C1OUT GP3/MCLR/VPP GP4/T1G/OSC2/CLKOUT GP5/T1CKI/OSC1/CLKIN VDD VSS Legend: Function Input Type Output Type GP0 TTL — General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up/pull-down. Selectable Ultra Low-Power Wake-up pin. Comparator 1 input – positive.
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PIC12F635/PIC16F636/639 TABLE 1-2: PIC16F636 PINOUT DESCRIPTIONS Name RA0/C1IN+/ICSPDAT/ULPWU RA1/C1IN-/VREF/ICSPCLK RA2/T0CKI/INT/C1OUT RA3/MCLR/VPP RA4/T1G/OSC2/CLKOUT RA5/T1CKI/OSC1/CLKIN RC0/C2IN+ RC1/C2IN- Function Input Type Output Type RA0 TTL — General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up/pull-down. Selectable Ultra Low-Power Wake-up pin. Comparator 1 input – positive.
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PIC12F635/PIC16F636/639 TABLE 1-3: PIC16F639 PINOUT DESCRIPTIONS Function Input Type Output Type LCCOM AN — Common reference for analog inputs. LCX LCX AN — 125 kHz analog X channel input. LCY LCY AN — 125 kHz analog Y channel input. LCZ LCZ AN — 125 kHz analog Z channel input. RA0/C1IN+/ICSPDAT/ULPWU RA0 TTL — General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up/pull-down. Selectable Ultra Low-Power Wake-up pin.
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PIC12F635/PIC16F636/639 TABLE 1-3: PIC16F639 PINOUT DESCRIPTIONS (CONTINUED) Name Function Input Type Output Type RC3/LFDATA/RSSI/CCLK/SDO RC3 TTL CMOS General purpose I/O. LFDATA — CMOS Digital output representation of analog input signal to LC pins. RSSI — Current Received signal strength indicator. Analog current that is proportional to input amplitude. Description CCLK — — SDIO TTL CMOS Input/Output for SPI communication. RC4 TTL CMOS General purpose I/O.
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PIC12F635/PIC16F636/639 2.0 MEMORY ORGANIZATION 2.1 Program Memory Organization The PIC12F635/PIC16F636/639 devices have a 13-bit program counter capable of addressing an 8K x 14 program memory space. Only the first 1K x 14 (0000h-03FFh, for the PIC12F635) and 2K x 14 (0000h-07FFh, for the PIC16F636/639) is physically implemented. Accessing a location above these boundaries will cause a wraparound within the first 2K x 14 space.
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PIC12F635/PIC16F636/639 2.2.1 GENERAL PURPOSE REGISTER The register file is organized as 64 x 8 for the PIC12F635 and 128 x 8 for the PIC16F636/639. Each register is accessed, either directly or indirectly, through the File Select Register, FSR (see Section 2.4 “Indirect Addressing, INDF and FSR Registers”). 2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFRs) are registers used by the CPU and peripheral functions for controlling the desired operation of the device (see Figure 2-1).
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PIC12F635/PIC16F636/639 FIGURE 2-3: PIC12F635 SPECIAL FUNCTION REGISTERS File Address Indirect addr.(1) 00h TMR0 01h PCL 02h STATUS 03h FSR 04h GPIO 05h 06h 07h 08h 09h PCLATH 0Ah INTCON 0Bh PIR1 0Ch 0Dh TMR1L 0Eh TMR1H 0Fh T1CON 10h 11h 12h 13h 14h 15h 16h 17h WDTCON 18h CMCON0 19h CMCON1 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h General Purpose Register 64 Bytes File Address Indirect addr.
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PIC12F635/PIC16F636/639 FIGURE 2-4: PIC16F636/639 SPECIAL FUNCTION REGISTERS File Address (1) Indirect addr. 00h TMR0 01h PCL 02h STATUS 03h FSR 04h PORTA 05h 06h PORTC 07h 08h 09h PCLATH 0Ah INTCON 0Bh PIR1 0Ch 0Dh TMR1L 0Eh TMR1H 0Fh T1CON 10h 11h 12h 13h 14h 15h 16h 17h WDTCON 18h CMCON0 19h CMCON1 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh General 20h Purpose Register 96 Bytes 7Fh Bank 0 File Address (1) Indirect addr.
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PIC12F635/PIC16F636/639 TABLE 2-1: Addr Name PIC12F635 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR/BOR/ WUR Page xxxx xxxx 32,137 Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 01h TMR0 Timer0 Module Register xxxx xxxx 61,137 02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 32,137 03h STATUS 04h FSR 05h GPIO IRP RP1 RP0 TO PD Z DC C
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PIC12F635/PIC16F636/639 TABLE 2-2: Addr PIC12F635 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR/BOR/ WUR Page xxxx xxxx 32,137 1111 1111 63,137 0000 0000 32,137 0001 1xxx 26,137 xxxx xxxx 32,137 Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 81h OPTION_REG 82h PCL RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Program Counter’s (PC) Least Significant Byte
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PIC12F635/PIC16F636/639 TABLE 2-3: Addr Name PIC16F636/639 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0 Value on POR/BOR/ WUR Page Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 32,137 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bank 0 00h INDF 01h TMR0 Timer0 Module Register xxxx xxxx 61,137 02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 32,137 03h STATUS 04h FSR 05h PORTA 06h 07h IRP RP1 RP0 TO
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PIC12F635/PIC16F636/639 TABLE 2-4: Addr PIC16F636/639 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR/BOR/ WUR Page xxxx xxxx 32,137 Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 81h OPTION_REG 82h PCL 83h STATUS 84h FSR 85h TRISA 86h 87h RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Program Counter’s (PC) Least Significant Byte IRP RP1 RP0 TO PD Z D
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PIC12F635/PIC16F636/639 TABLE 2-5: Addr Name PIC12F635/PIC16F636/639 SPECIAL FUNCTION REGISTERS SUMMARY BANK 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR/BOR/ WUR Page Bank 2 10Ch — Unimplemented — — 10Dh — Unimplemented — — 10Eh — Unimplemented — — 10Fh — Unimplemented — — 110h CRCON GO/DONE ENC/DEC 111h CRDAT0(2) Cryptographic Data Register 0 0000 0000 0000 0000 112h CRDAT1(2) Cryptographic Data Register 1 0000 0000 0000 0000 113h CRDAT2(2) Crypt
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PIC12F635/PIC16F636/639 2.2.2.1 STATUS Register The STATUS register, shown in Register 2-1, contains: • the arithmetic status of the ALU • the Reset status • the bank select bits for data memory (GPR and SFR) The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic.
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PIC12F635/PIC16F636/639 2.2.2.2 OPTION Register Note: The OPTION register is a readable and writable register which contains various control bits to configure: • • • • TMR0/WDT prescaler External RA2/INT interrupt TMR0 Weak pull-up/pull-downs on PORTA REGISTER 2-2: To achieve a 1:1 prescaler assignment for Timer0, assign the prescaler to the WDT by setting the PSA bit of the OPTION register to ‘1’. See Section 5.1.3 “Software Programmable Prescaler”.
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PIC12F635/PIC16F636/639 2.2.2.3 INTCON Register Note: The INTCON register is a readable and writable register which contains the various enable and flag bits for TMR0 register overflow, PORTA change and external RA2/INT pin interrupts. REGISTER 2-3: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE of the INTCON register.
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PIC12F635/PIC16F636/639 2.2.2.4 PIE1 Register The PIE1 register contains the interrupt enable bits, as shown in Register 2-4. REGISTER 2-4: Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.
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PIC12F635/PIC16F636/639 2.2.2.5 PIR1 Register The PIR1 register contains the interrupt flag bits, as shown in Register 2-5. REGISTER 2-5: R/W-0 Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
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PIC12F635/PIC16F636/639 2.2.2.6 PCON Register The Power Control (PCON) register (see Table 12-3) contains flag bits to differentiate between a: • • • • • Power-on Reset (POR) Wake-up Reset (WUR) Brown-out Reset (BOR) Watchdog Timer Reset (WDT) External MCLR Reset The PCON register also controls the Ultra Low-Power Wake-up and software enable of the BOR. The PCON register bits are shown in Register 2-6.
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PIC12F635/PIC16F636/639 2.3 2.3.2 PCL and PCLATH The Program Counter (PC) is 13 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 2-5 shows the two situations for the loading of the PC. The upper example in Figure 2-5 shows how the PC is loaded on a write to PCL (PCLATH<4:0> → PCH).
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PIC12F635/PIC16F636/639 FIGURE 2-6: DIRECT/INDIRECT ADDRESSING PIC12F635/PIC16F636/639 Direct Addressing RP1 RP0 Bank Select 6 Indirect Addressing From Opcode 0 IRP 7 Bank Select Location Select 00 01 10 File Select Register 0 Location Select 11 00h 180h Data Memory 7Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 Note: For memory map detail, see Figure 2-2. © 2007 Microchip Technology Inc.
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PIC12F635/PIC16F636/639 3.0 OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR) The Oscillator module can be configured in one of eight clock modes. 3.1 Overview 1. 2. 3. The Oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 3-1 illustrates a block diagram of the Oscillator module. 4. 5.
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PIC12F635/PIC16F636/639 3.2 Oscillator Control The Oscillator Control (OSCCON) register (Figure 3-1) controls the system clock and frequency selection options.
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PIC12F635/PIC16F636/639 3.3 Clock Source Modes Clock Source modes can be classified as external or internal. External Clock Modes 3.4.1 OSCILLATOR START-UP TIMER (OST) If the Oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) counts 1024 oscillations from OSC1. This occurs following a Power-on Reset (POR) and when the Power-up Timer (PWRT) has expired (if configured), or a wake-up from Sleep.
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PIC12F635/PIC16F636/639 3.4.3 LP, XT, HS MODES The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure 3-3). The mode selects a low, medium or high gain setting of the internal inverter-amplifier to support various resonator types and speed. LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current consumption is the least of the three modes. This mode is designed to drive only 32.
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PIC12F635/PIC16F636/639 3.4.4 EXTERNAL RC MODES 3.5 The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. There are two modes: RC and RCIO. In RC mode, the RC circuit connects to OSC1. OSC2/CLKOUT outputs the RC oscillator frequency divided by 4.
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PIC12F635/PIC16F636/639 3.5.2.1 OSCTUNE Register The HFINTOSC is factory calibrated but can be adjusted in software by writing to the OSCTUNE register (Register 3-2). The default value of the OSCTUNE register is ‘0’. The value is a 5-bit two’s complement number. REGISTER 3-2: When the OSCTUNE register is modified, the HFINTOSC frequency will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred.
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PIC12F635/PIC16F636/639 3.5.3 LFINTOSC The Low-Frequency Internal Oscillator (LFINTOSC) is an uncalibrated 31 kHz internal clock source. The output of the LFINTOSC connects to a postscaler and multiplexer (see Figure 3-1). Select 31 kHz, via software, using the IRCF<2:0> bits of the OSCCON register. See Section 3.5.4 “Frequency Select Bits (IRCF)” for more information. The LFINTOSC is also the frequency for the Power-up Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM).
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PIC12F635/PIC16F636/639 FIGURE 3-6: INTERNAL OSCILLATOR SWITCH TIMING LF(1) HF HFINTOSC LFINTOSC (FSCM and WDT disabled) HFINTOSC Start-up Time 2-cycle Sync Running LFINTOSC ≠0 IRCF <2:0> =0 System Clock Note 1: When going from LF to HF.
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PIC12F635/PIC16F636/639 3.6 Clock Switching The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bit of the OSCCON register. 3.6.1 SYSTEM CLOCK SELECT (SCS) BIT The System Clock Select (SCS) bit of the OSCCON register selects the system clock source that is used for the CPU and peripherals.
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PIC12F635/PIC16F636/639 3.7.3 CHECKING TWO-SPEED CLOCK STATUS Checking the state of the OSTS bit of the OSCCON register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Word register (CONFIG), or the internal oscillator. FIGURE 3-7: TWO-SPEED START-UP HFINTOSC TOST OSC1 0 1 1022 1023 OSC2 Program Counter PC - N PC PC + 1 System Clock DS41232D-page 44 © 2007 Microchip Technology Inc.
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PIC12F635/PIC16F636/639 3.8 3.8.3 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator fail. The FSCM can detect oscillator failure any time after the Oscillator Start-up Timer (OST) has expired. The FSCM is enabled by setting the FCMEN bit in the Configuration Word register (CONFIG). The FSCM is applicable to all external oscillator modes (LP, XT, HS, EC, RC and RCIO).
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PIC12F635/PIC16F636/639 FIGURE 3-9: FSCM TIMING DIAGRAM Sample Clock Oscillator Failure System Clock Output Clock Monitor Output (Q) Failure Detected OSFIF Test Note: Test The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity.
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PIC12F635/PIC16F636/639 4.0 I/O PORTS 4.2 Additional Pin Functions There are as many as twelve general purpose I/O pins available. Depending on which peripherals are enabled, some or all of the pins may not be available as general purpose I/O. In general, when a peripheral is enabled, the associated pin may not be used as a general purpose I/O pin. Every PORTA pin on the PIC12F635/PIC16F636/639 has an interrupt-on-change option and a weak pull-up/pull-down option.
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PIC12F635/PIC16F636/639 REGISTER 4-1: PORTA: PORTA REGISTER U-0 U-0 R/W-x R/W-x R-x R/W-x R/W-x R/W-x — — RA5 RA4 RA3 RA2 RA1 RA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RA<5:0>: PORTA I/O Pin bit 1 = Port pin is > VIH 0 = Port pin is < VIL REGISTER 4-2: x = Bit is unknown TRISA: PORTA TRI-STATE REGISTER U-0 U-0 R/W-1 R/W-1 R
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PIC12F635/PIC16F636/639 REGISTER 4-3: WDA: WEAK PULL-UP/PULL-DOWN DIRECTION REGISTER U-0 U-0 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1 — — WDA5 WDA4 — WDA2 WDA1 WDA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 WDA<5:4>: Pull-up/Pull-down Selection bits 1 = Pull-up selected 0 = Pull-down selected bit 3 Unimplemented: Read as ‘0’ bit 2-0 WDA<2
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PIC12F635/PIC16F636/639 4.2.2 INTERRUPT-ON-CHANGE Each of the PORTA pins is individually configurable as an interrupt-on-change pin. Control bits, IOCAx, enable or disable the interrupt function for each pin. Refer to Register 4-5. The interrupt-on-change is disabled on a Power-on Reset. For enabled interrupt-on-change pins, the values are compared with the old value latched on the last read of PORTA.
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PIC12F635/PIC16F636/639 4.2.3 ULTRA LOW-POWER WAKE-UP The Ultra Low-Power Wake-up (ULPWU) on RA0 allows a slow falling voltage to generate an interrupt-on-change on RA0 without excess current consumption. The mode is selected by setting the ULPWUE bit of the PCON register. This enables a small current sink which can be used to discharge a capacitor on RA0.
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PIC12F635/PIC16F636/639 4.2.4 PIN DESCRIPTIONS AND DIAGRAMS 4.2.4.1 Figure 4-2 shows the diagram for this pin. The RA0 pin is configurable to function as one of the following: Each PORTA pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions, such as the comparator, refer to the appropriate section in this data sheet.
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PIC12F635/PIC16F636/639 4.2.4.2 RA1/C1IN-/VREF/ICSPCLK 4.2.4.3 RA2/T0CKI/INT/C1OUT Figure 4-2 shows the diagram for this pin. The RA1 pin is configurable to function as one of the following: Figure 4-3 shows the diagram for this pin.
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PIC12F635/PIC16F636/639 4.2.4.4 RA3/MCLR/VPP Figure 4-4 shows the diagram for this pin.
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PIC12F635/PIC16F636/639 4.2.4.5 4.2.4.6 RA4/T1G/OSC2/CLKOUT RA5/T1CKI/OSC1/CLKIN Figure 4-5 shows the diagram for this pin. The RA4 pin is configurable to function as one of the following: Figure 4-6 shows the diagram for this pin.
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PIC12F635/PIC16F636/639 TABLE 4-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR, WUR Value on all other Resets PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --xx xx00 --uu uu00 INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 000x 0000 000x TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1
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PIC12F635/PIC16F636/639 4.3 EXAMPLE 4-3: PORTC PORTC is a general purpose I/O port consisting of 6 bidirectional pins. The pins can be configured for either digital I/O or analog input to comparator. For specific information about individual functions, refer to the appropriate section in this data sheet. Note: The CMCON0 register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read ‘0’.
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PIC12F635/PIC16F636/639 4.3.1 RC0/C2IN+ Figure 4-7 shows the diagram for this pin. The RC0 pin is configurable to function as one of the following: FIGURE 4-7: Data Bus • a general purpose I/O • an analog input to the comparator 4.3.2 RC1/C2IN- D WR PORTC 4.3.3 RC2 Figure 4-8 shows the diagram for this pin. The RC2 pin is configurable to function as a general purpose I/O. 4.3.4 RC3 RC5 Figure 4-8 shows the diagram for this pin. The RC5 pin is configurable to function as a general purpose I/O.
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PIC12F635/PIC16F636/639 4.3.6 RC4/C2OUT Figure 4-9 shows the diagram for this pin.
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PIC12F635/PIC16F636/639 5.0 TIMER0 MODULE 5.1 Timer0 Operation The Timer0 module is an 8-bit timer/counter with the following features: When used as a timer, the Timer0 module can be used as either an 8-bit timer or an 8-bit counter. • • • • • 5.1.
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PIC12F635/PIC16F636/639 5.1.3 SOFTWARE PROGRAMMABLE PRESCALER A single software programmable prescaler is available for use with either Timer0 or the Watchdog Timer (WDT), but not both simultaneously. The prescaler assignment is controlled by the PSA bit of the OPTION register. To assign the prescaler to Timer0, the PSA bit must be cleared to a ‘0’. There are 8 prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION register.
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PIC12F635/PIC16F636/639 REGISTER 5-1: OPTION_REG: OPTION REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 RAPU: PORTA Pull-up Enable bit 1 = PORTA pull-ups are disabled 0 = PORTA pull-ups are enabled by individual PORT latch values bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt
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PIC12F635/PIC16F636/639 6.
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PIC12F635/PIC16F636/639 FIGURE 6-1: TIMER1 BLOCK DIAGRAM TMR1GE T1GINV TMR1ON Set flag bit TMR1IF on Overflow To C2 Comparator Module Timer1 Clock TMR1(2) TMR1H TMR1L Synchronized clock input 0 EN 1 Oscillator (1) T1SYNC OSC1/T1CKI 1 Prescaler 1, 2, 4, 8 Synchronize(3) det 0 OSC2/T1G 2 T1CKPS<1:0> TMR1CS 1 INTOSC Without CLKOUT T1OSCEN FOSC FOSC/4 Internal Clock 1 0 CxOUT 0 T1GSS T1ACS Note 1: 2: 3: ST Buffer is low power type when using LP osc, or high speed type when using T1CKI.
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PIC12F635/PIC16F636/639 6.2.1 INTERNAL CLOCK SOURCE When the internal clock source is selected the TMR1H:TMR1L register pair will increment on multiples of TCY as determined by the Timer1 prescaler. 6.2.2 EXTERNAL CLOCK SOURCE When the external clock source is selected, the Timer1 module may work as a timer or a counter. When counting, Timer1 is incremented on the rising edge of the external clock input T1CKI.
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PIC12F635/PIC16F636/639 6.7 Timer1 Interrupt The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set these bits: • Timer1 interrupt enable bit of the PIE1 register • PEIE bit of the INTCON register • GIE bit of the INTCON register The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine. Note: 6.8 6.
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PIC12F635/PIC16F636/639 6.10 Timer1 Control Register The Timer1 Control register (T1CON), shown in Register 6-1, is used to control Timer1 and select the various features of the Timer1 module.
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PIC12F635/PIC16F636/639 TABLE 6-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets CMCON1 — — — — — — T1GSS CMSYNC ---- --10 00-- --10 INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 000x 0000 000x PIE1 EEIE LVDIE CRIE C2IE(1) C1IE OSFIE — TMR1IE 000- 00-0 000- 00-0 PIR1 EEIF LVDIF CRIF C2IF(1) C1IF OSFIF — TMR1IF 000- 00-0 000- 00-0 xxxx xxxx uuuu uuuu xx
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PIC12F635/PIC16F636/639 7.0 COMPARATOR MODULE comparator is a digital low level. When the analog voltage at VIN+ is greater than the analog voltage at VIN-, the output of the comparator is a digital high level. Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes.
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PIC12F635/PIC16F636/639 FIGURE 7-3: COMPARATOR C1 OUTPUT BLOCK DIAGRAM (PIC16F636/639) MULTIPLEX Port Pins C1INV To C1OUT pin C1 D Q1 To Data Bus Q EN RD CMCON0 Set C1IF bit D Q3*RD CMCON0 Q EN CL Reset Note 1: 2: FIGURE 7-4: Q1 and Q3 are phases of the four-phase system clock (FOSC). Q1 is held high during Sleep mode.
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PIC12F635/PIC16F636/639 7.2 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 7-5. Since the analog input pins share their connection with a digital input, they have reverse biased ESD protection diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur.
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PIC12F635/PIC16F636/639 7.3 Comparator Configuration There are eight modes of operation for the comparator. The CM<2:0> bits of the CMCON0 register are used to select these modes as shown in Figures 7-6 and 7-7.
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PIC12F635/PIC16F636/639 FIGURE 7-7: COMPARATOR I/O OPERATING MODES (PIC16F636/639) Comparators Reset (POR Default Value) CM<2:0> = 000 A VINC1INVIN+ C1IN+ A C2IN- C1 Off(1) C2 (1) Two Independent Comparators CM<2:0> = 100 VINC1IN- A C1IN+ VIN- A VIN+ C2IN+ A C2INOff C2IN+ Three Inputs Multiplexed to Two Comparators CM<2:0> = 001 C1INC1IN+ C2INC2IN+ A A VIN- CIS = 0 CIS = 1 VIN+ C1 C1OUT C2 C2OUT VIN- A VIN+ A C1INC1IN+ A A VIN- CIS = 0 CIS = 1 VIN+ C1 C1IN+ C2IN+ C2IN-
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PIC12F635/PIC16F636/639 7.4 7.4.3 Comparator Control COMPARATOR INPUT SWITCH The CMCON0 register (Register 7-1) provides access to the following comparator features: The inverting input of the comparators may be switched between two analog pins in the following modes: • • • • PIC12F635 Mode selection Output state Output polarity Input switch 7.4.
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PIC12F635/PIC16F636/639 7.5 Comparator Response Time The comparator output is indeterminate for a period of time after the change of an input source or the selection of a new reference voltage. This period is referred to as the response time. The response time of the comparator differs from the settling time of the voltage reference. Therefore, both of these times must be considered when determining the total response time to a comparator input change.
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PIC12F635/PIC16F636/639 FIGURE 7-8: COMPARATOR INTERRUPT TIMING W/O CMCON0 READ Q1 Q3 CIN+ TRT CxOUT Set CxIF (level) CxIF reset by software FIGURE 7-9: COMPARATOR INTERRUPT TIMING WITH CMCON0 READ Q1 Q3 CIN+ TRT CxOUT Set CxIF (level) CxIF cleared by CMCON0 read reset by software Note 1: If a change in the CMCON0 register (CxOUT) should occur when a read operation is being executed (start of the Q2 cycle), then the CxIF of the PIR1 register interrupt flag may not get set.
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PIC12F635/PIC16F636/639 7.7 Operation During Sleep 7.8 The comparator, if enabled before entering Sleep mode, remains active during Sleep. The additional current consumed by the comparator is shown separately in the Section 15.0 “Electrical Specifications”. If the comparator is not used to wake the device, power consumption can be minimized while in Sleep mode by turning off the comparator. The comparator is turned off by selecting mode CM<2:0> = 000 or CM<2:0> = 111 of the CMCON0 register.
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PIC12F635/PIC16F636/639 REGISTER 7-2: CMCON0: COMPARATOR CONFIGURATION REGISTER (PIC16F636/639) R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 C2OUT: Comparator 2 Output bit When C2INV = 0: 1 = C2 VIN+ > C2 VIN0 = C2 VIN+ < C2 VINWhen C2INV = 1: 1 = C2 VIN+ < C2 VIN0 = C2 VIN+ > C2 VIN- bit 6 C
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PIC12F635/PIC16F636/639 7.9 Comparator Gating Timer1 This feature can be used to time the duration or interval of analog events. Clearing the T1GSS bit of the CMCON1 register will enable Timer1 to increment based on the output of the comparator (or Comparator C2 for PIC16F636/639). This requires that Timer1 is on and gating is enabled. See Section 6.0 “Timer1 Module with Gate Control” for details.
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PIC12F635/PIC16F636/639 REGISTER 7-3: CMCON1: COMPARATOR CONFIGURATION REGISTER (PIC12F635) U-0 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 — — — — — — T1GSS CMSYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-2 Unimplemented: Read as ‘0’ bit 1 T1GSS: Timer1 Gate Source Select bit(1) 1 = Timer1 Gate Source is T1G pin (pin should be configured as digital input) 0 = Ti
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PIC12F635/PIC16F636/639 7.11 Comparator Voltage Reference The Comparator Voltage Reference module provides an internally generated voltage reference for the comparators. The following features are available: • • • • • Independent from Comparator operation Two 16-level voltage ranges Output clamped to VSS Ratiometric with VDD Fixed Voltage Reference The VRCON register (Register 7-5) controls the Voltage Reference module shown in Figure 7-10. 7.11.
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PIC12F635/PIC16F636/639 REGISTER 7-5: VRCON: VOLTAGE REFERENCE CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 VREN — VRR — VR3 VR2 VR1 VR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 VREN: CVREF Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down, no IDD drain and CVREF = VSS.
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PIC12F635/PIC16F636/639 TABLE 7-2: Name SUMMARY OF REGISTERS ASSOCIATED WITH THE COMPARATOR AND VOLTAGE REFERENCE MODULES Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets -0-0 0000 CMCON0 — COUT — CINV CIS CM2 CM1 CM0 -0-0 0000 CMCON1 — — — — — — T1GSS CMSYNC ---- --10 ---- --10 INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 000x 0000 000x PIE1 EEIE LVDIE CRIE — C1IE OSFIE — TMR1IE 000- 00-0 000- 00-0 PIR1
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PIC12F635/PIC16F636/639 8.0 PROGRAMMABLE LOW-VOLTAGE DETECT (PLVD) MODULE The Programmable Low-Voltage Detect (PLVD) module is a power supply detector which monitors the internal power supply. This module is typically used in key fobs and other devices, where certain actions need to be taken as a result of a falling battery voltage.
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PIC12F635/PIC16F636/639 8.1 PLVD Operation To setup the PLVD for operation, the following steps must be taken: • Enable the module by setting the LVDEN bit of the LVDCON register. • Configure the trip point by setting the LVDL<2:0> bits of the LVDCON register. • Wait for the reference voltage to become stable. Refer to Section 8.4 “Stable Reference Indication”. • Clear the LVDIF bit of the PIRx register. The LVDIF bit will be set when VDD falls below the PLVD trip point.
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PIC12F635/PIC16F636/639 REGISTER 8-1: LVDCON: LOW-VOLTAGE DETECT CONTROL REGISTER U-0 U-0 — R-0 (1) — IRVST R/W-0 U-0 R/W-1 R/W-0 R/W-0 LVDEN — LVDL2 LVDL1 LVDL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5 IRVST: Internal Reference Voltage Stable Status Flag bit(1) 1 = Indicates that the PLVD is stable and PLVD interrup
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PIC12F635/PIC16F636/639 9.0 DATA EEPROM MEMORY The EEPROM data memory allows byte read and write. A byte write automatically erases the location and writes the new data (erase before write). The EEPROM data memory is rated for high erase/write cycles. The write time is controlled by an on-chip timer. The write time will vary with voltage and temperature as well as from chip-to-chip. Please refer to A/C specifications in Section 15.0 “Electrical Specifications” for exact limits.
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PIC12F635/PIC16F636/639 9.1 EECON1 AND EECON2 Registers EECON1 is the control register with four low-order bits physically implemented. The upper four bits are non-implemented and read as ‘0’s. Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set in software. They are cleared in hardware at completion of the read or write operation. The inability to clear the WR bit in software prevents the accidental, premature termination of a write operation.
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PIC12F635/PIC16F636/639 9.2 Reading the EEPROM Data Memory To read a data memory location, the user must write the address to the EEADR register and then set control bit RD of the EECON1 register, as shown in Example 9-1. The data is available, in the very next cycle, in the EEDAT register. Therefore, it can be read in the next instruction. EEDAT holds this value until another read, or until it is written to by the user (during a write operation). EXAMPLE 9-1: BANKSEL MOVLW MOVWF BSF MOVF 9.
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PIC12F635/PIC16F636/639 9.5 Protection Against Spurious Write 9.6 There are conditions when the user may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built in. On power-up, WREN is cleared. Also, the Power-up Timer (nominal 64 ms duration) prevents EEPROM write.
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PIC12F635/PIC16F636/639 10.0 KEELOQ® COMPATIBLE CRYPTOGRAPHIC MODULE To obtain information regarding the implementation of the KEELOQ module, Microchip Technology requires the execution of the “KEELOQ® Encoder License Agreement”. The “KEELOQ® Encoder License Agreement” may be accessed through the Microchip web site located at www.microchip.com/KEELOQ. Further information may be obtained by contacting your local Microchip Sales Representative. © 2007 Microchip Technology Inc.
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PIC12F635/PIC16F636/639 11.0 ANALOG FRONT-END (AFE) FUNCTIONAL DESCRIPTION (PIC16F639 ONLY) The PIC16F639 device consists of the PIC16F636 device and low frequency (LF) Analog Front-End (AFE), with the AFE section containing three analog-input channels for signal detection and LF talk-back. This section describes the Analog Front-End (AFE) in detail.
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PIC12F635/PIC16F636/639 11.6 AGC Control 11.10 Demodulator The AGC controls the variable attenuator to limit the internal signal voltage to avoid saturation of internal amplifiers and demodulators (Refer to Section 11.4 “Variable Attenuator”). The Demodulator consists of a full-wave rectifier, low pass filter, peak detector and Data Slicer that detects the envelope of the input signal.
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PIC12F635/PIC16F636/639 11.14.2 INACTIVITY TIMER The timer is reset when the: The Inactivity Timer is used to automatically return the AFE to Standby mode, if there is no input signal. The time-out period is approximately 16 ms (TINACT), based on the 32 kHz internal clock. • CS pin is low (any SPI command). • Output enable filter is disabled. • LFDATA pin is enabled (signal passed output enable filter).
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PIC12F635/PIC16F636/639 FIGURE 11-1: FUNCTIONAL BLOCK DIAGRAM – ANALOG FRONT-END ÷ 64 AGC LCX Detector RF Lim Tune X Sensitivity Control X Mod WAKEX A ÷ 64 LCCOM WAKEY Σ AGC LCY Detector RF Lim Tune Y Sensitivity Control Y Mod WAKEZ A LCCOM ÷ 64 AGC LCZ Detector RF Lim Tune Z Sensitivity Control Z Mod Watchdog A B Modulation Depth LCCOM To Sensitivity X To Sensitivity Y To Sensitivity Z 32 kHZ Oscillator AGC Timer Output Enable Filter AGC Preserve Command Decoder/Controlle
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© 2007 Microchip Technology Inc. MOD FET Decode Capacitor Tuning PD = Peak Detector LPF = Low-pass Filter FWR = Full-wave Rectifier FGA = Fixed Gain Amplifier Legend: Registers Configuration > 4 VPP RF Limiter A Sens. Control FGA1 Low-Pass Filter Demodulator Full-Wave Rectifier Var Atten Z Y X REF GEN + – Peak Detector FGA2 A DETX DETY DETZ Detector Data Slicer AUTOCHSEL + – ≈ 0.
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PIC12F635/PIC16F636/639 FIGURE 11-3: BIDIRECTIONAL PASSIVE KEYLESS ENTRY (PKE) SYSTEM APPLICATION EXAMPLE d Encrypte Codes se Respon (UHF) LED LED UHF Transmitter Microcontroller (MCU) UHF Receiver Ant. X mand LF Com z) k (125 H PIC16F639 MCU (PIC16F636) Ant. Y LF Transmitter/ Receiver + Ant.
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PIC12F635/PIC16F636/639 11.15 Configurable Output Enable Filter The purpose of this filter is to enable the LFDATA output and wake the microcontroller only after receiving a specific sequence of pulses on the LC input pins. Therefore, it prevents the AFE from waking up the microcontroller due to noise or unwanted input signals. The circuit compares the timing of the demodulated header waveform with a pre-defined value, and enables the demodulated LFDATA output when a match occurs.
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PIC12F635/PIC16F636/639 FIGURE 11-6: OUTPUT ENABLE FILTER TIMING EXAMPLE (DETAILED) Start bit LFDATA Output LF Coil Input 3.
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PIC12F635/PIC16F636/639 TABLE 11-1: TYPICAL OUTPUT ENABLE FILTER TIMING If the filter resets due to a long high (TOEH > TOET), the high-pulse timer will not begin timing again until after a gap of TE and another low-to-high transition occurs on the demodulator output.
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PIC12F635/PIC16F636/639 TABLE 11-2: INPUT SENSITIVITY VS. MODULATED SIGNAL STRENGTH SETTING (AGCSIG <7>) AGCSIG<7> (Config. Register 5) Input Sensitivity (Typical) Description 0 Disabled – the AFE passes signal of any amplitude level it is capable of detecting (demodulated data and carrier clock). 3.0 mVPP 1 Enabled – No output until AGC Status = 1 (i.e., VPEAK ≈ 20 mVPP) (demodulated data and carrier clock). • Provides the best signal to noise ratio. 20 mVPP 11.
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PIC12F635/PIC16F636/639 11.20 Soft Reset TABLE 11-3: The AFE issues a Soft Reset in the following events: a) b) c) d) After Power-on Reset (POR), After Inactivity timer time-out, If an “Abort” occurs, After receiving SPI Soft Reset command. The “Abort” occurs if there is no positive signal detected at the end of the AGC stabilization period (TAGC). The Soft Reset initializes internal circuits and brings the AFE into a low current Standby mode operation.
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PIC12F635/PIC16F636/639 FIGURE 11-7: MODULATION DEPTH EXAMPLES (a) Modulation Depth Definition Amplitude Modulation Depth (%) = B t A-B A X 100% A (b) LFDATA Output vs. Input vs.
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PIC12F635/PIC16F636/639 11.22 Low-Current Sleep Mode 11.25 Error Detection of AFE Configuration Register Data The Sleep command from the microcontroller, via an SPI Interface command, places the AFE into an ultra Low-current mode. All circuits including the RF Limiter, except the minimum circuitry required to retain register memory and SPI capability, will be powered down to minimize the AFE current draw. Power-on Reset or any SPI command, other than Sleep command, is required to wake the AFE from Sleep.
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PIC12F635/PIC16F636/639 11.26 Factory Calibration 11.28 Battery Back-up and Batteryless Operation Microchip calibrates the AFE to reduce the device-to-device variation in standby current, internal timing and sensitivity, as well as channel-to-channel sensitivity variation. The device supports both battery back-up and batteryless operation by the addition of external components, allowing the device to be partially or completely powered from the field. 11.
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PIC12F635/PIC16F636/639 11.29 Demodulator The demodulator recovers the modulation data from the received signal, containing carrier plus data, by appropriate envelope detection. The demodulator has a fast rise (charge) time (TDR) and a fall time (TDF) appropriate to an envelope of input signal (see Section 15.0 “Electrical Specifications” for TDR and TDF specifications). The demodulator contains the full-wave rectifier, low-pass filter, peak detector and data slicer.
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PIC12F635/PIC16F636/639 Case I. When Output Enable Filter is disabled: Demodulated output is available immediately after the AGC stabilization time (TAGC). Figure 11-10 shows an example of demodulated output when the Output Enable Filter is disabled. FIGURE 11-10: INPUT SIGNAL AND DEMODULATOR OUTPUT WHEN THE OUTPUT ENABLE FILTER IS DISABLED Input Signal LFDATA Output Case II.
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PIC12F635/PIC16F636/639 FIGURE 11-11: INPUT SIGNAL AND DEMODULATOR OUTPUT (WHEN OUTPUT ENABLE FILTER IS ENABLED AND INPUT MEETS FILTER TIMING REQUIREMENTS) Input Signal LFDATA Output FIGURE 11-12: NO DEMODULATOR OUTPUT (WHEN OUTPUT ENABLE FILTER IS ENABLED BUT INPUT DOES NOT MEET FILTER TIMING REQUIREMENTS) Input Signal No LFDATA Output © 2007 Microchip Technology Inc.
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PIC12F635/PIC16F636/639 11.31.2 CARRIER CLOCK OUTPUT When the Carrier Clock output is selected, the LFDATA output is a square pulse of the input carrier clock and available as soon as the AGC stabilization time (TAGC) is completed. There are two Configuration register options for the carrier clock output: (a) clock divide-by one or (b) clock divide-by four, depending on bit DATOUT<7> of Configuration Register 2 (Register 11-3). The carrier clock output is available immediately after the AGC settling time.
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PIC12F635/PIC16F636/639 FIGURE 11-13: CARRIER CLOCK OUTPUT EXAMPLES (A) CARRIER CLOCK OUTPUT WITH CARRIER/1 OPTION Carrier Clock Output Carrier Input (B) CARRIER CLOCK OUTPUT WITH CARRIER/4 OPTION Carrier Clock Output Carrier Input © 2007 Microchip Technology Inc.
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PIC12F635/PIC16F636/639 11.31.3 RECEIVED SIGNAL STRENGTH INDICATOR (RSSI) OUTPUT An analog current is available at the LFDATA pin when the Received Signal Strength Indicator (RSSI) output is selected for the AFE’s Configuration register. The analog current is linearly proportional to the input signal strength (see Figure 11-15). All timers in the circuit, such as inactivity timer, alarm timer, and AGC settling time, are disabled during the RSSI mode.
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PIC12F635/PIC16F636/639 FIGURE 11-15: RSSI OUTPUT CURRENT VS. INPUT SIGNAL LEVEL EXAMPLE 90 RSSI Output Current (uA) 80 70 60 50 40 30 20 10 0 0 1 2 3 4 5 6 7 8 9 10 Input Voltage (V PP) © 2007 Microchip Technology Inc.
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PIC12F635/PIC16F636/639 ANALOG-TO-DIGITAL DATA CONVERSION OF RSSI SIGNAL The AFE’s RSSI output is an analog current. It needs an external Analog-to-Digital (ADC) data conversion device for digitized output. The ADC data conversion can be accomplished by using a stand-alone external ADC device or by firmware utilizing MCU’s internal comparator along with a few external resistors and a capacitor.
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PIC12F635/PIC16F636/639 FIGURE 11-17: SPI WRITE SEQUENCE TCSH 2 1 LFDATA (output) SDI (input) 3 LSb 1/FSCLK TSU MCU pin still Input LFDATA/RSSI/ CCLK/SDIO MSb SCLK (input) TCS1 Driven low by MCU ALERT (output) TSCCS THD 5 MCU pin to Input ALERT 4 16 Clocks for Write Command, Address and Data THI TLO MCU pin to Output SCLK/ Driven low by MCU TCSSC 7 ALERT (output) TCS0 Driven low by MCU CS MCU pin to Input 6 LFDATA (output) MCU SPI Write Details: 1. 2. 3. 4. 5. 6. 7.
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PIC12F635/PIC16F636/639 SPI READ SEQUENCE TCSH TCSH 1 LSb ALERT (output) 1/FSCLK 8 16 Clocks for Read Result 10 TCSSC TCS1 SCLK (input) ALERT (output) TCS0 MCU pin still Input TSU THD LFDATA/RSSI/ CCLK/SDIO LFDATA (output) MSb SCLK (input) TCSSC SDI (input) MCU pin to Input ALERT (output) MCU pin to Output SCLK/ALERT Driven low by MCU THI TLO TCS0 Driven low by MCU TSCCS TCS1 Driven low by MCU 16 Clocks for Read Command, Address and Dummy Data MCU pin to Input 4 TCSSC 7 Driv
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PIC12F635/PIC16F636/639 11.32.2 COMMAND DECODER/CONTROLLER The circuit executes 8 SPI commands from the MCU. The command structure is: Command (3 bits) + Configuration Address (4 bits) + Data Byte and Row Parity Bit received by the AFE Most Significant bit first. Table 11-5 shows the available SPI commands. TABLE 11-5: The AFE operates in SPI mode 0,0. In mode 0,0 the clock idles in the low state (Figure 11-19).
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PIC12F635/PIC16F636/639 FIGURE 11-19: DETAILED SPI INTERFACE TIMING (AFE) CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SCLK MSb LSb Command 11.32.2.1 Clamp On Command Clamp Off Command This command results in de-activating (turning off) the modulation transistors of all channels. 11.32.2.3 Sleep Command This command places the AFE in Sleep mode – minimizing current draw by disabling all but the essential circuitry. Any other command wakes the AFE (example: Clamp Off command). 11.32.
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PIC12F635/PIC16F636/639 TABLE 11-6: ANALOG FRONT-END CONFIGURATION REGISTERS SUMMARY Register Name Address Configuration Register 0 0000 Configuration Register 1 0001 Configuration Register 2 0010 Configuration Register 3 0011 Configuration Register 4 0100 Configuration Register 5 0101 Column Parity Register 6 0110 AFE Status Register 7 0111 REGISTER 11-1: Bit 8 Bit 7 Bit 6 OEH Bit 5 OEL DATOUT RSSIFET CLKDIV Unimplemented Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ALRTIND LCZEN LCYEN
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PIC12F635/PIC16F636/639 REGISTER 11-2: CONFIGURATION REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DATOUT1 DATOUT0 LCXTUN5 LCXTUN4 LCXTUN3 LCXTUN2 LCXTUN1 LCXTUN0 R1PAR bit 8 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 8-7 DATOUT<1:0>: LFDATA Output type bit 00 = Demodulated output 01 = Carrier Clock output 10 = RSSI output 11 = RSSI output b
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PIC12F635/PIC16F636/639 REGISTER 11-4: CONFIGURATION REGISTER 3 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — LCZTUN5 LCZTUN4 LCZTUN3 LCZTUN2 LCZTUN1 LCZTUN0 R3PAR bit 8 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 8-7 Unimplemented: Read as ‘0’ bit 6-1 LCZTUN<5:0>: LCZ Tuning Capacitance bit 000000 = +0 pF (Default) : 111111 = +63 pF bit 0 R3PAR: Reg
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PIC12F635/PIC16F636/639 REGISTER 11-6: CONFIGURATION REGISTER 5 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 AUTOCHSEL AGCSIG MODMIN1 MODMIN0 LCZSEN3 LCZSEN2 LCZSEN1 LCZSEN0 R5PAR bit 8 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 8 AUTOCHSEL: Auto Channel Select bit 1 = Enabled – AFE selects channel(s) that has demodulator output “high” at the end of TS
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PIC12F635/PIC16F636/639 REGISTER 11-8: AFE STATUS REGISTER 7 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 CHZACT CHYACT CHXACT AGCACT WAKEZ WAKEY WAKEX ALARM PEI bit 8 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 8 CHZACT: Channel Z Active(1) bit (cleared via Soft Reset) 1 = Channel Z is passing data after TAGC 0 = Channel Z is not passing data after TAGC bit 7 CHYACT:
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PIC12F635/PIC16F636/639 12.0 SPECIAL FEATURES OF THE CPU The PIC12F635/PIC16F636/639 has a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving features and offer code protection.
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PIC12F635/PIC16F636/639 REGISTER 12-1: — CONFIG: CONFIGURATION WORD REGISTER — — FCMEN WURE IESO BOREN1 BOREN0 bit 15 bit 8 CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit P = Programmable’ U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘1’ bit 12 WURE: Wake-up Reset Enable bit 1 = Standard wake-up and continue enabled 0 = Wake-up and
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PIC12F635/PIC16F636/639 12.2 Reset They are not affected by a WDT wake-up since this is viewed as the resumption of normal operation. TO and PD bits are set or cleared differently in different Reset situations, as indicated in Table 12-3. These bits are used in software to determine the nature of the Reset. See Table 12-4 for a full description of Reset states of all registers.
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PIC12F635/PIC16F636/639 12.3 Power-on Reset The on-chip POR circuit holds the chip in Reset until VDD has reached a high enough level for proper operation. To take advantage of the POR, simply connect the MCLR pin through a resistor to VDD. This will eliminate external RC components usually needed to create Power-on Reset. A maximum rise time for VDD is required. See Section 15.0 “Electrical Specifications” for details. If the BOR is enabled, the maximum rise time specification does not apply.
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PIC12F635/PIC16F636/639 FIGURE 12-2: RECOMMENDED MCLR CIRCUIT VDD R1 1 kΩ (or greater) PIC12F635/PIC16F636/639 MCLR C1 0.1 μF (optional, not critical) © 2007 Microchip Technology Inc.
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PIC12F635/PIC16F636/639 12.6 Brown-out Reset (BOR) The BOREN0 and BOREN1 bits in the Configuration Word register select one of four BOR modes. Two modes have been added to allow software or hardware control of the BOR enable. When BOREN<1:0> = 01, the SBOREN bit of the PCON register enables/disables the BOR allowing it to be controlled in software. By selecting BOREN<1:0>, the BOR is automatically disabled in Sleep to conserve power and enabled on wake-up. In this mode, the SBOREN bit is disabled.
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PIC12F635/PIC16F636/639 12.7 Time-out Sequence 12.8 On power-up, the time-out sequence is as follows: first, PWRT time-out is invoked after POR has expired, then OST is activated after the PWRT time-out has expired. The total time-out will vary based on oscillator Configuration and PWRTE bit status. For example, in EC mode with PWRTE bit erased (PWRT disabled), there will be no time-out at all. Figure 12-4, Figure 12-5 and Figure 12-6 depict time-out sequences.
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PIC12F635/PIC16F636/639 FIGURE 12-4: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR) VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset FIGURE 12-5: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR) VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset FIGURE 12-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD) VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset DS41232D-page 136 © 2007 Microchip Technology Inc.
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PIC12F635/PIC16F636/639 TABLE 12-4: Register W INITIALIZATION CONDITION FOR REGISTERS Address Power-on Reset Wake-up Reset MCLR Reset WDT Reset Brown-out Reset(1) Wake-up Reset Wake-up from Sleep through Interrupt Wake-up from Sleep through WDT Time-out — xxxx xxxx uuuu uuuu uuuu uuuu INDF 00h/80h xxxx xxxx xxxx xxxx uuuu uuuu TMR0 01h xxxx xxxx uuuu uuuu uuuu uuuu PCL 02h/82h 0000 0000 0000 0000 PC + 1(3) STATUS 03h/83h 0001 1xxx 000q quuu(4) uuuq quuu(4) FSR 04h/84h xxxx xx
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PIC12F635/PIC16F636/639 TABLE 12-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS Program Counter Status Register PCON Register Power-on Reset 000h 0001 1xxx --01 --0x MCLR Reset during normal operation 000h 000u uuuu --0u --uu MCLR Reset during Sleep 000h 0001 0uuu --0u --uu WDT Reset 000h 0000 uuuu --0u --uu PC + 1 uuu0 0uuu --uu --uu 000h 0001 1uuu --01 --10 PC + 1 uuu1 0uuu --uu --uu 000h 0001 1xxx --01 --0x Condition WDT Wake-up Brown-out Reset Interrupt Wake-up from S
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PIC12F635/PIC16F636/639 12.9 Interrupts The PIC12F635/PIC16F636/639 has multiple interrupt sources: • • • • • • • External Interrupt RA2/INT Timer0 Overflow Interrupt PORTA Change Interrupts 2 Comparator Interrupts Timer1 Overflow Interrupt EEPROM Data Write Interrupt Fail-Safe Clock Monitor Interrupt The Interrupt Control register (INTCON) and Peripheral Interrupt Request Register 1 (PIR1) record individual interrupt requests in flag bits.
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PIC12F635/PIC16F636/639 12.9.2 TIMER INTERRUPT 12.9.3 An overflow (FFh → 00h) in the TMR0 register will set the T0IF bit of the INTCON register. The interrupt can be enabled/disabled by setting/clearing T0IE bit of the INTCON register. See Section 5.0 “Timer0 Module” for operation of the Timer0 module. An input change on PORTA change sets the RAIF bit of the INTCON register. The interrupt can be enabled/disabled by setting/clearing the RAIE bit of the INTCON register.
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PIC12F635/PIC16F636/639 FIGURE 12-8: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT(3) (4) INT pin (1) (1) (5) INTF Flag (INTCON<1>) Interrupt Latency(2) GIE bit (INTCON<7>) Instruction Flow PC Instruction Fetched Instruction Executed Note 1: PC + 1 PC + 1 0004h Inst (PC) Inst (PC + 1) — Inst (0004h) Inst (0005h) Inst (PC – 1) Inst (PC) Dummy Cycle Dummy Cycle Inst (0004h) PC 0005h INTF flag is sampled here (every
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PIC12F635/PIC16F636/639 12.10 Context Saving During Interrupts Note: During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt (e.g., W and STATUS registers). This must be implemented in software. The PIC12F635/PIC16F636/639 normally does not require saving the PCLATH. However, if computed GOTO’s are used in the ISR and the main code, the PCLATH must be saved and restored in the ISR.
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PIC12F635/PIC16F636/639 12.11 Watchdog Timer (WDT) The PIC12F635/PIC16F636/639 WDT is code and functionally compatible with other PIC16F WDT modules and adds a 16-bit prescaler to the WDT. This allows the user to have a scaler value for the WDT and TMR0 at the same time. In addition, the WDT time-out value can be extended to 268 seconds. WDT is cleared under certain conditions described in Table 12-7. 12.11.1 WDT OSCILLATOR The WDT derives its time base from the 31 kHz LFINTOSC.
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PIC12F635/PIC16F636/639 REGISTER 12-2: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 U-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4-1 WDTPS<3:0>: Watchdog Timer Period Select bits Bit Value = Prescale Rate 0000 = 1:32 0001 = 1:64 0010 = 1:128 0011 = 1:256 0100 = 1
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PIC12F635/PIC16F636/639 12.12 Power-Down Mode (Sleep) The Power-down mode is entered by executing a SLEEP instruction. If the Watchdog Timer is enabled: • • • • • WDT will be cleared but keeps running. PD bit in the STATUS register is cleared. TO bit is set. Oscillator driver is turned off. I/O ports maintain the status they had before SLEEP was executed (driving high, low or high-impedance).
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PIC12F635/PIC16F636/639 FIGURE 12-10: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(2) CLKOUT(4) INT pin INTF Flag (INTCON<1>) Interrupt Latency(3) GIE bit (INTCON<7>) Processor in Sleep INSTRUCTION FLOW PC PC Instruction Fetched Instruction Executed Note PC + 1 PC + 2 PC + 2 Inst(PC) = Sleep Inst(PC + 1) Inst(PC + 2) Inst(PC – 1) Sleep Inst(PC + 1) PC + 2 Dummy Cycle 0004h 0005h Inst(0004h) Inst(0005h) Dumm
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PIC12F635/PIC16F636/639 12.15 In-Circuit Serial Programming 12.16 In-Circuit Debugger The PIC12F635/PIC16F636/639 microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data and three other lines for: Since in-circuit debugging requires the loss of clock, data and MCLR pins, MPLAB® ICD 2 development with a 14-pin device is not practical.
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PIC12F635/PIC16F636/639 13.
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PIC12F635/PIC16F636/639 TABLE 13-2: PIC12F635/PIC16F636/639 INSTRUCTION SET Mnemonic, Operands 14-Bit Opcode Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f – f, d f, d f, d f, d f, d f, d f, d f – f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclu
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PIC12F635/PIC16F636/639 13.2 Instruction Descriptions ADDLW Add literal and W Syntax: [ label ] ADDLW Operands: 0 ≤ k ≤ 255 Operation: (W) + k → (W) Status Affected: C, DC, Z Description: The contents of the W register are added to the eight-bit literal ‘k’ and the result is placed in the W register. k BCF Bit Clear f Syntax: [ label ] BCF Operands: 0 ≤ f ≤ 127 0≤b≤7 Operation: 0 → (f) Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared.
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PIC12F635/PIC16F636/639 BTFSS Bit Test f, Skip if Set CLRWDT Clear Watchdog Timer Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRWDT Operands: 0 ≤ f ≤ 127 0≤b<7 Operands: None Operation: 00h → WDT 0 → WDT prescaler, 1 → TO 1 → PD Status Affected: TO, PD Description: CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set.
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PIC12F635/PIC16F636/639 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) - 1 → (destination); skip if result = 0 Operation: (f) + 1 → (destination), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in the W register.
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PIC12F635/PIC16F636/639 MOVF Move f Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] MOVF f,d MOVWF Move W to f Syntax: [ label ] MOVWF Operands: 0 ≤ f ≤ 127 Operation: (W) → (f) f Operation: (f) → (dest) Status Affected: None Status Affected: Z Description: Description: The contents of register f is moved to a destination dependent upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself.
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PIC12F635/PIC16F636/639 RETFIE Return from Interrupt RETLW Return with literal in W Syntax: [ label ] Syntax: [ label ] Operands: None Operands: 0 ≤ k ≤ 255 Operation: TOS → PC, 1 → GIE Operation: k → (W); TOS → PC Status Affected: None Status Affected: None Description: Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction.
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PIC12F635/PIC16F636/639 RLF Rotate Left f through Carry SLEEP Enter Sleep mode Syntax: [ label ] Syntax: [ label ] SLEEP Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: None Operation: Operation: See description below Status Affected: C Description: The contents of register ‘f’ are rotated one bit to the left through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’.
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PIC12F635/PIC16F636/639 SUBWF Subtract W from f XORLW Exclusive OR literal with W Syntax: [ label ] SUBWF f,d Syntax: [ label ] XORLW k Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ k ≤ 255 (f) - (W) → (destination) Operation: (W) .XOR. k → (W) Operation: Status Affected: Z Description: The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register.
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PIC12F635/PIC16F636/639 14.
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PIC12F635/PIC16F636/639 14.2 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging.
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PIC12F635/PIC16F636/639 14.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment.
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PIC12F635/PIC16F636/639 14.11 PICSTART Plus Development Programmer 14.13 Demonstration, Development and Evaluation Boards The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins.
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PIC12F635/PIC16F636/639 15.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings(†) Ambient temperature under bias....................................................................................................... -40°C to +125°C Storage temperature ........................................................................................................................ -65°C to +150°C Voltage on VDD with respect to VSS .....................................................................................
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PIC12F635/PIC16F636/639 PIC12F635/16F636 VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C FIGURE 15-1: 5.5 5.0 VDD (V) 4.5 4.0 3.5 3.0 2.5 2.0 0 4 8 10 20 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Cross-hatched area is for HFINTOSC and EC modes only. PIC16F639 VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +85°C FIGURE 15-2: 5.5 5.0 VDD (V) 4.5 4.0 3.6 3.0 2.5 2.
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PIC12F635/PIC16F636/639 FIGURE 15-3: HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE 125 ± 5% Temperature (°C) 85 ± 2% 60 ± 1% 25 0 -40 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) © 2007 Microchip Technology Inc.
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PIC12F635/PIC16F636/639 15.1 DC Characteristics: PIC12F635/PIC16F636-I (Industrial) PIC12F635/PIC16F636-E (Extended) DC CHARACTERISTICS Param No. Sym VDD Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Min Typ† Max Units Conditions Supply Voltage D001 D001A D001B D001C 2.0 2.0 3.0 4.5 — — — — 5.5 5.5 5.5 5.
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PIC12F635/PIC16F636/639 15.2 DC Characteristics: PIC12F635/PIC16F636-I (Industrial) DC CHARACTERISTICS Param No. D010 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Conditions Sym Device Characteristics Min Typ† Max Units VDD IDD Supply Current(1,2) D011 D012 D013 D014 D015 D016 D017 D018 D019 — 11 16 μA 2.0 — 18 28 μA 3.0 — 35 54 μA 5.0 — 140 240 μA 2.0 — 220 380 μA 3.0 — 380 550 μA 5.
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PIC12F635/PIC16F636/639 15.2 DC Characteristics: PIC12F635/PIC16F636-I (Industrial) (Continued) DC CHARACTERISTICS Param No. D020 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Conditions Sym Device Characteristics Min Typ† Max Units VDD IPD D021 D022A D022B D023 D024A D024B D025 Power-down Base Current(4) 1.2 μA 2.0 0.20 1.5 μA 3.0 0.35 1.8 μA 5.0 — 1.0 2.2 μA 2.0 — 2.0 4.0 μA 3.0 — 3.0 7.0 μA 5.
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PIC12F635/PIC16F636/639 15.3 DC Characteristics: PIC12F635/PIC16F636-E (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C for extended DC CHARACTERISTICS Param No. D010E Conditions Sym Device Characteristics Min Typ† Max Units VDD IDD Supply Current D011E D012E D013E D014E D015E D016E D017E D018E D019E (1,2) — 11 16 μA 2.0 — 18 28 μA 3.0 — 35 54 μA 5.0 — 140 240 μA 2.0 — 220 380 μA 3.0 — 380 550 μA 5.
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PIC12F635/PIC16F636/639 15.3 DC Characteristics: PIC12F635/PIC16F636-E (Extended) (Continued) DC CHARACTERISTICS Param No. D020 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C for extended Conditions Sym IPD D021 D022A D022B D023 D024A D024B D025 Device Characteristics Power-down Base Current(4) Min Typ† Max Units VDD Note WDT, BOR, Comparators, VREF and T1OSC disabled — 0.15 1.2 μA 2.0 — 0.20 1.5 μA 3.0 — 0.35 1.8 μA 5.
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PIC12F635/PIC16F636/639 15.4 DC Characteristics: PIC12F635/PIC16F636-I (Industrial) PIC12F635/PIC16F636-E (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended DC CHARACTERISTICS Param No. Sym VIL Characteristic Min Typ† Max Units Conditions VSS — 0.8 V VSS — 0.15 VDD V Otherwise VSS — 0.2 VDD V Entire range VSS — 0.2 VDD V VSS — 0.3 V VSS — 0.3 VDD V 2.0 (0.25 VDD + 0.
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PIC12F635/PIC16F636/639 15.4 DC Characteristics: PIC12F635/PIC16F636-I (Industrial) PIC12F635/PIC16F636-E (Extended) (Continued) DC CHARACTERISTICS Param No. Sym VOH Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Min Typ† Max Units Conditions Output High Voltage D090 I/O ports VDD – 0.7 — — V IOH = -3.0 mA, VDD = 4.5V (Ind.) D092 OSC2/CLKOUT (RC mode) VDD – 0.
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PIC12F635/PIC16F636/639 15.5 DC Characteristics: PIC16F639-I (Industrial) DC CHARACTERISTICS Param No. Sym Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Min Typ† Max Units Conditions D001 VDD Supply Voltage 2.0 — 3.6 V FOSC ≤ 10 MHz D001A VDDT Supply Voltage (AFE) 2.0 — 3.6 V Analog Front-End VDD voltage. Treated as VDD in this document. D002 VDR RAM Data Retention Voltage(1) 1.
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PIC12F635/PIC16F636/639 15.6 DC Characteristics: PIC16F639-I (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Supply Voltage 2.0V ≤ VDD ≤ 3.6V DC CHARACTERISTICS Param No.
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PIC12F635/PIC16F636/639 15.7 DC Characteristics: PIC16F639-I (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Supply Voltage 2.0V ≤ VDD ≤ 3.6V DC CHARACTERISTICS Param No. Sym VIL Characteristic Min Typ† Max Units Conditions Input Low Voltage I/O ports: D030A with TTL buffer VSS — 0.15 VDD V D031 with Schmitt Trigger buffer VSS — 0.2 VDD V V D032 MCLR, OSC1 (RC mode) VSS — 0.
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PIC12F635/PIC16F636/639 15.7 DC Characteristics: PIC16F639-I (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Supply Voltage 2.0V ≤ VDD ≤ 3.6V DC CHARACTERISTICS Param No. Sym VOH Characteristic Min Typ† Max Units Conditions Output High Voltage D090 I/O ports VDD – 0.7 — — V IOH = -3.0 mA, VDD = 3.6V (Ind.) D092 OSC2/CLKOUT (RC mode) VDD – 0.7 — — V IOH = -1.3 mA, VDD = 3.6V (Ind.) IOH = -1.
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PIC12F635/PIC16F636/639 15.8 Thermal Considerations Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Para m No. Sym TH01 θJA TH02 TH03 TH04 TH05 TH06 TH07 Note Characteristic Thermal Resistance Junction to Ambient Typ Units 84.6 163.0 52.4 52.4 69.8 85.0 100.4 46.3 108.1 41.2 38.8 3.0 3.0 32.5 31.0 31.7 2.6 32.
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PIC12F635/PIC16F636/639 15.9 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2.
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PIC12F635/PIC16F636/639 15.10 AC Characteristics: PIC12F635/PIC16F636/639 (Industrial, Extended) FIGURE 15-5: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1/CLKIN OS02 OS04 OS04 OS03 OSC2/CLKOUT (LP, XT, HS Modes) OSC2/CLKOUT (CLKOUT Mode) TABLE 15-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Param No.
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PIC12F635/PIC16F636/639 TABLE 15-2: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No. Sym Characteristic Freq Tolerance Min Typ† Max Units Conditions OS06 TWARM Internal Oscillator Switch when running(3) — — — 2 TOSC Slowest clock OS07 TSC Fail-Safe Sample Clock Period(1) — — 21 — ms LFINTOSC/64 OS08 HFOSC Internal Calibrated HFINTOSC Frequency(2) ±1% 7.92 8.0 8.08 MHz VDD = 3.
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PIC12F635/PIC16F636/639 FIGURE 15-6: CLKOUT AND I/O TIMING Cycle Write Fetch Read Execute Q4 Q1 Q2 Q3 FOSC OS12 OS11 OS20 OS21 CLKOUT OS19 OS18 OS16 OS13 OS17 I/O pin (Input) OS14 OS15 I/O pin (Output) New Value Old Value OS18, OS19 TABLE 15-3: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No.
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PIC12F635/PIC16F636/639 FIGURE 15-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Start-Up Time Internal Reset(1) Watchdog Timer Reset(1) 31 34 34 I/O pins Note 1: Asserted low.
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PIC12F635/PIC16F636/639 TABLE 15-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No.
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PIC12F635/PIC16F636/639 FIGURE 15-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 49 47 TMR0 or TMR1 TABLE 15-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No.
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PIC12F635/PIC16F636/639 TABLE 15-6: COMPARATOR SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No. Sym Characteristics Min Typ† Max Units CM01 VOS Input Offset Voltage — ± 5.0 ± 10 mV CM02 VCM Input Common Mode Voltage 0 — VDD – 1.
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PIC12F635/PIC16F636/639 TABLE 15-9: PIC16F639 PLVD CHARACTERISTICS: Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +85°C Operating Voltage VDD Range 2.0V-5.5V DC CHARACTERISTICS Sym. Characteristic PLVD Voltage VPLVD *TPLVDS Min Typ† Max Units LVDL<2:0> = 001 1.900 2.0 2.100 V LVDL<2:0> = 010 2.000 2.1 2.200 V LVDL<2:0> = 011 2.100 2.2 2.300 V LVDL<2:0> = 100 2.200 2.3 2.400 V LVDL<2:0> = 101 3.825 4.0 4.175 V LVDL<2:0> = 110 4.
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PIC12F635/PIC16F636/639 15.11 AC Characteristics: Analog Front-End for PIC16F639 (Industrial) AC CHARACTERISTICS Param No. AF01 Sym. VSENSE Standard Operating Conditions (unless otherwise stated) Supply Voltage 2.0V ≤ VDD ≤ 3.6V Operating temperature -40°C ≤ TAMB ≤ +85°C for industrial LC Signal Input Sinusoidal 300 mVPP Carrier Frequency 125 kHz LCCOM connected to VSS Characteristic Min Typ† Max Units 1 3.
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PIC12F635/PIC16F636/639 15.11 AC Characteristics: Analog Front-End for PIC16F639 (Industrial) (Continued) AC CHARACTERISTICS Param No. Sym. Standard Operating Conditions (unless otherwise stated) Supply Voltage 2.0V ≤ VDD ≤ 3.6V Operating temperature -40°C ≤ TAMB ≤ +85°C for industrial LC Signal Input Sinusoidal 300 mVPP Carrier Frequency 125 kHz LCCOM connected to VSS Characteristic Min Typ† Max Units Conditions AF14 TLFDATAR Rise time of LFDATA — 0.5 — μs VDD = 3.
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PIC12F635/PIC16F636/639 15.11 AC Characteristics: Analog Front-End for PIC16F639 (Industrial) (Continued) AC CHARACTERISTICS Param No. Sym. AF30 TOET Characteristic AF32 * † Note 1: 2: IRSSI IRSSILR Min Typ† Max Units Maximum output enable filter period OEH 01 01 01 01 OEL 00 = 01 = 10 = 11 = 10 10 10 10 00 01 10 11 11 11 11 11 00 01 10 11 00 AF31 Standard Operating Conditions (unless otherwise stated) Supply Voltage 2.0V ≤ VDD ≤ 3.
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PIC12F635/PIC16F636/639 15.12 SPI Timing: Analog Front-End (AFE) for PIC16F639 AC CHARACTERISTICS Param Sym Standard Operating Conditions (unless otherwise stated) Supply Voltage 2.0V ≤ VDD ≤ 3.
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PIC12F635/PIC16F636/639 16.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range.
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PIC12F635/PIC16F636/639 FIGURE 16-2: MAXIMUM IDD vs. FOSC OVER VDD (EC MODE) EC Mode 4.0 3.5 Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp) + 3σ (-40°C to 125°C) 5.5V 5.0V 3.0 IDD (mA) 2.5 4.0V 2.0 3.0V 1.5 2.0V 1.0 0.5 0.0 1 MHz 2 MHz 4 MHz 6 MHz 8 MHz 10 MHz 12 MHz 14 MHz 16 MHz 18 MHz 20 MHz FOSC FIGURE 16-3: TYPICAL IDD vs. FOSC OVER VDD (HS MODE) Typical IDD vs FOSC Over Vdd HS Mode 4.0 3.
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PIC12F635/PIC16F636/639 FIGURE 16-4: MAXIMUM IDD vs. FOSC OVER VDD (HS MODE) Maximum IDD vs FOSC Over Vdd HS Mode 5.0 4.5 4.0 Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp) + 3σ (-40°C to 125°C) 5.5V IDD (mA) 3.5 5.0V 3.0 4.5V 2.5 2.0 1.5 4.0V 3.5V 3.0V 1.0 0.5 0.0 4 MHz 10 MHz 16 MHz 20 MHz FOSC FIGURE 16-5: TYPICAL IDD vs.
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PIC12F635/PIC16F636/639 FIGURE 16-6: MAXIMUM IDD vs. VDD OVER FOSC (XT MODE) XT Mode 1,400 Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp) + 3σ (-40°C to 125°C) 1,200 IDD (μA) 1,000 800 4 MHz 600 400 1 MHz 200 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 5.0 5.5 VDD (V) FIGURE 16-7: TYPICAL IDD vs.
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PIC12F635/PIC16F636/639 FIGURE 16-8: MAXIMUM IDD vs. VDD OVER FOSC (EXTRC MODE) EXTRC Mode 1,400 Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp) + 3σ (-40°C to 125°C) 1,200 IDD (μA) 1,000 4 MHz 800 600 1 MHz 400 200 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 5.0 5.5 VDD (V) FIGURE 16-9: IDD vs.
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PIC12F635/PIC16F636/639 FIGURE 16-10: IDD vs. VDD OVER FOSC (LP MODE) LP Mode 70 Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp) + 3σ (-40°C to 125°C) 60 50 IDD (μA) 32 kHz Maximum 40 30 32 kHz Typical 20 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 16-11: TYPICAL IDD vs. FOSC OVER VDD (HFINTOSC MODE) HFINTOSC 1,600 1,400 Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp) + 3σ (-40°C to 125°C) 5.5V 5.0V 1,200 IDD (μA) 1,000 4.0V 800 3.
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PIC12F635/PIC16F636/639 FIGURE 16-12: MAXIMUM IDD vs. FOSC OVER VDD (HFINTOSC MODE) HFINTOSC 2,000 1,800 Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp) + 3σ (-40°C to 125°C) 5.5V 5.0V 1,600 1,400 4.0V IDD (μA) 1,200 1,000 3.0V 800 600 2.0V 400 200 0 125 kHz 250 kHz 500 kHz 1 MHz 2 MHz 4 MHz 8 MHz FOSC FIGURE 16-13: TYPICAL IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) Typical (Sleep Mode all Peripherals Disabled) 0.45 0.
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PIC12F635/PIC16F636/639 FIGURE 16-14: MAXIMUM IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) Maximum (Sleep Mode all Peripherals Disabled) 18.0 16.0 Typical: Statistical Mean @25°C Maximum: 3σ Case Temp) + 3σ Maximum: Mean Mean + (Worst (-40°C to 125°C) 14.0 Max. 125°C IPD (μA) 12.0 10.0 8.0 6.0 4.0 Max. 85°C 2.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 16-15: COMPARATOR IPD vs.
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PIC12F635/PIC16F636/639 FIGURE 16-16: BOR IPD vs. VDD OVER TEMPERATURE 160 140 Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp) + 3σ (-40°C to 125°C) 120 IPD (μA) 100 Maximum 80 Typical 60 40 20 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 16-17: TYPICAL WDT IPD vs. VDD OVER TEMPERATURE Typical 3.0 2.5 Typical: Statistical StatisticalMean Mean @25°C @25°C Typical: Maximum: Mean (Worst Case Temp) + 3σ (-40°C to 125°C) IPD (μA) 2.0 1.5 1.0 0.5 0.0 2.0 2.5 3.0 3.
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PIC12F635/PIC16F636/639 FIGURE 16-18: MAXIMUM WDT IPD vs. VDD OVER TEMPERATURE Maximum 25.0 20.0 IPD (μA) Max. 125°C 15.0 Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp) + 3σ (-40°C to 125°C) 10.0 Max. 85°C 5.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 16-19: WDT PERIOD vs. VDD OVER TEMPERATURE 30 28 Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp) + 3σ (-40°C to 125°C) Max. (125°C) 26 Max.
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PIC12F635/PIC16F636/639 FIGURE 16-20: WDT PERIOD vs. TEMPERATURE OVER VDD (5.0V) Vdd = 5V 30 28 Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp) + 3σ (-40°C to 125°C) 26 Maximum 24 Time (ms) 22 20 Typical 18 16 Minimum 14 12 10 -40°C 25°C 85°C 125°C Temperature (°C) FIGURE 16-21: CVREF IPD vs. VDD OVER TEMPERATURE (HIGH RANGE) High Range 140 120 Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp) + 3σ (-40°C to 125°C) 100 IPD (μA) Max. 125°C 80 Max.
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PIC12F635/PIC16F636/639 FIGURE 16-22: CVREF IPD vs. VDD OVER TEMPERATURE (LOW RANGE) 180 Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp) + 3σ (-40°C to 125°C) 160 140 120 IPD (μA) Max. 125°C 100 Max. 85°C 80 Typical 60 40 20 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 16-23: VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V) (VDD = 3V, -40×C TO 125×C) 0.8 0.7 Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp) + 3σ (-40°C to 125°C) Max. 125°C 0.6 VOL (V) 0.
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PIC12F635/PIC16F636/639 FIGURE 16-24: VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V) 0.45 Typical: Statistical Mean @25°C Typical: Statistical @25×C+ 3σ Maximum: Mean (Worst Mean Case Temp) Maximum: Meas(-40×C + 3 to 125×C) (-40°C to 125°C) 0.40 Max. 125°C 0.35 Max. 85°C VOL (V) 0.30 0.25 Typ. 25°C 0.20 0.15 Min. -40°C 0.10 0.05 0.00 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 IOL (mA) FIGURE 16-25: VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V) 3.5 3.0 Max. -40°C Typ. 25°C 2.5 Min.
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PIC12F635/PIC16F636/639 FIGURE 16-26: VOH vs. IOH OVER TEMPERATURE (VDD = 5.0V) (VDD = 5V, -40×C TO 125×C) 5.5 5.0 Max. -40°C Typ. 25°C VOH (V) 4.5 Min. 125°C 4.0 3.5 Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp) + 3σ (-40°C to 125°C) 3.0 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 -5.0 IOH (mA) FIGURE 16-27: TTL INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE (TTL Input, -40×C TO 125×C) 1.7 1.
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PIC12F635/PIC16F636/639 FIGURE 16-28: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE (ST Input, -40×C TO 125×C) 4.0 VIH Max. 125°C 3.5 Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp) + 3σ (-40°C to 125°C) VIH Min. -40°C VIN (V) 3.0 2.5 2.0 VIL Max. -40°C 1.5 VIL Min. 125°C 1.0 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 16-29: T1OSC IPD vs. VDD OVER TEMPERATURE (32 kHz) 45.0 40.
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PIC12F635/PIC16F636/639 FIGURE 16-30: COMPARATOR RESPONSE TIME (RISING EDGE) 531 806 1000 900 Max. 125°C Response Time (nS) 800 700 600 Note: 500 VCM = VDD - 1.5V)/2 V+ input = VCM V- input = Transition from VCM + 100MV to VCM - 20MV Max. 85°C 400 300 Typ. 25°C 200 Min. -40°C 100 0 2.0 2.5 4.0 5.5 VDD (V) FIGURE 16-31: COMPARATOR RESPONSE TIME (FALLING EDGE) 1000 900 Max. 125°C 800 Response Time (nS) 700 600 Note: 500 VCM = VDD - 1.
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PIC12F635/PIC16F636/639 FIGURE 16-32: LFINTOSC FREQUENCY vs. VDD OVER TEMPERATURE (31 kHz) LFINTOSC 31Khz 45,000 40,000 Max. -40°C 35,000 Typ. 25°C Frequency (Hz) 30,000 25,000 20,000 Min. 85°C Min. 125°C 15,000 10,000 Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp) + 3σ (-40°C to 125°C) 5,000 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 16-33: TYPICAL HFINTOSC START-UP TIMES vs.
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PIC12F635/PIC16F636/639 FIGURE 16-34: MAXIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE -40C to +85C 25 Typical: Statistical Mean @25°C Maximum: Mean (Worst Case Temp) + 3σ (-40°C to 125°C) Time (μs) 20 15 85°C 25°C 10 -40°C 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 16-35: MINIMUM HFINTOSC START-UP TIMES vs.
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PIC12F635/PIC16F636/639 FIGURE 16-36: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (25°C) 5 4 Change from Calibration (%) 3 2 1 0 -1 -2 -3 -4 -5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 16-37: TYPICAL HFINTOSC FREQUENCY CHANGE OVER DEVICE VDD (85°C) 5 4 Change from Calibration (%) 3 2 1 0 -1 -2 -3 -4 -5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) © 2007 Microchip Technology Inc.
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PIC12F635/PIC16F636/639 FIGURE 16-38: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (125°C) 5 4 Change from Calibration (%) 3 2 1 0 -1 -2 -3 -4 -5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 16-39: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (-40°C) 5 4 Change from Calibration (%) 3 2 1 0 -1 -2 -3 -4 -5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS41232D-page 210 © 2007 Microchip Technology Inc.
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PIC12F635/PIC16F636/639 17.0 PACKAGING INFORMATION 17.1 Package Marking Information 8-Lead PDIP Example 12F635/P e3 017 0610 XXXXXXXX XXXXXNNN YYWW 8-Lead SOIC Example 12F635/ SN e3 0610 017 XXXXXXXX XXXXYYWW NNN 8-Lead DFN (4x4x0.9 mm) XXXXXX XXXXXX YYWW NNN PIC12F 635/MF 0610 017 8-Lead DFN-S (6x5 mm) XXXXXXX XXXXXXX XXYYWW NNN Legend: XX...
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PIC12F635/PIC16F636/639 17.1 Package Marking Information (Continued) 14-Lead PDIP XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN 14-Lead SOIC XXXXXXXXXXX XXXXXXXXXXX YYWWNNN 14-Lead TSSOP XXXXXXXX YYWW NNN 16-Lead QFN XXXXXXX XXXXXXX YYWWNNN 20-Lead SSOP XXXXXXXXXXX XXXXXXXXXXX YYWWNNN DS41232D-page 212 Example PIC16F636-I/P 0610017 Example PIC16F636 -I/SL e3 0610017 Example F636/ST 0610 017 Example 16F636 -I/ML 0610017 Example PIC16F639 -I/SS e3 0610017 © 2007 Microchip Technology Inc.
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PIC12F635/PIC16F636/639 17.2 Package Details The following sections give the technical details of the packages. 8-Lead Plastic Dual In-Line (P or PA) – 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 3 2 D E A2 A L A1 c e eB b1 b Units Dimension Limits Number of Pins INCHES MIN N NOM MAX 8 Pitch e Top to Seating Plane A – – .
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PIC12F635/PIC16F636/639 8-Lead Plastic Small Outline (SN or OA) – Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D e N E E1 NOTE 1 1 2 3 α h b h A2 A c φ L A1 L1 Units Dimension Limits Number of Pins β MILLIMETERS MIN N NOM MAX 8 Pitch e Overall Height A – 1.27 BSC – Molded Package Thickness A2 1.25 – – Standoff § A1 0.10 – 0.
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PIC12F635/PIC16F636/639 8-Lead Plastic Dual Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D e b N N L E E2 K EXPOSED PAD 2 2 1 NOTE 1 1 NOTE 1 D2 TOP VIEW BOTTOM VIEW A3 A A1 NOTE 2 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 8 Pitch e Overall Height A 0.80 0.90 1.00 Standoff A1 0.00 0.02 0.
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PIC12F635/PIC16F636/639 8-Lead Plastic Dual Flat, No Lead Package (MF) – 6x5 mm Body [DFN-S] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging e D L b N N K E E2 EXPOSED PAD NOTE 1 1 2 2 NOTE 1 1 D2 BOTTOM VIEW TOP VIEW A A3 A1 NOTE 2 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 8 Pitch e Overall Height A 0.80 1.27 BSC 0.85 1.00 Standoff A1 0.00 0.01 0.
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PIC12F635/PIC16F636/639 14-Lead Plastic Dual In-Line (P or PD) – 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 3 2 D E A2 A L A1 c b1 b e eB Units Dimension Limits Number of Pins INCHES MIN N NOM MAX 14 Pitch e Top to Seating Plane A – – .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .
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PIC12F635/PIC16F636/639 14-Lead Plastic Small Outline (SL or OD) – Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 3 e h b A A2 c φ L A1 β L1 Units Dimension Limits Number of Pins α h MILLIMETERS MIN N NOM MAX 14 Pitch e Overall Height A – 1.27 BSC – Molded Package Thickness A2 1.25 – – Standoff § A1 0.10 – 0.
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PIC12F635/PIC16F636/639 14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 e b A2 A c A1 φ Units Dimension Limits Number of Pins L L1 MILLIMETERS MIN N NOM MAX 14 Pitch e Overall Height A – 0.65 BSC – Molded Package Thickness A2 0.80 1.00 1.05 Standoff A1 0.05 – 0.15 1.
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PIC12F635/PIC16F636/639 16-Lead Plastic Quad Flat, No Lead Package (ML) – 4x4x0.9 mm Body [QFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D2 D EXPOSED PAD e E E2 2 2 1 b 1 TOP VIEW K N N NOTE 1 L BOTTOM VIEW A3 A A1 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 16 Pitch e Overall Height A 0.80 0.65 BSC 0.90 1.00 Standoff A1 0.00 0.02 0.
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PIC12F635/PIC16F636/639 20-Lead Plastic Shrink Small Outline (SS) – 5.30 mm Body [SSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 b e c A2 A φ A1 L1 Units Dimension Limits Number of Pins L MILLIMETERS MIN N NOM MAX 20 Pitch e Overall Height A – 0.65 BSC – 2.00 Molded Package Thickness A2 1.65 1.75 1.85 Standoff A1 0.05 – – Overall Width E 7.40 7.80 8.
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PIC12F635/PIC16F636/639 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
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PIC12F635/PIC16F636/639 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
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PIC12F635/PIC16F636/639 APPENDIX A: DATA SHEET REVISION HISTORY Revision A This is a new data sheet. Revision B Added PIC16F639 to the data sheet. Revision C (12/2006) Added Characterization data; Updated Package Drawings; Added Comparator Voltage Reference section. Revision D (03/2007) Replaced Package Drawings (Rev. AM); Replaced Development Support Section. Updated Product ID System. © 2007 Microchip Technology Inc.
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PIC12F635/PIC16F636/639 INDEX A Absolute Maximum Ratings .............................................. 163 AC Characteristics Analog Front-End (AFE) for PIC16F639 ................... 187 Industrial and Extended ............................................ 179 Load Conditions ........................................................ 178 AGC Settling ....................................................................... 99 Analog Front-End Configuration Registers Summary Table ...............................
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PIC12F635/PIC16F636/639 INTOSC .............................................................. 39 INTOSCIO........................................................... 39 LFINTOSC .......................................................... 41 Clock Switching................................................................... 43 CMCON0 Register .............................................................. 80 CMCON1 Register ..............................................................
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PIC12F635/PIC16F636/639 Internal Oscillator Block INTOSC Specifications............................................ 180, 181 Internet Address................................................................ 223 Interrupts ........................................................................... 139 Associated Registers ................................................ 141 Comparator ................................................................. 77 Context Saving...........................................
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PIC12F635/PIC16F636/639 Column Parity Register 6 .................................. 126 Configuration Register 0 ................................... 123 Configuration Register 1 ................................... 124 Configuration Register 2 ................................... 124 Configuration Register 3 ................................... 125 Configuration Register 4 ................................... 125 Configuration Register 5 ................................... 126 CMCON0 (Comparator Control 0) ....
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PIC12F635/PIC16F636/639 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Device Temperature Range Package Pattern Examples: a) b) Device: PIC12F635(1, 2), PIC16F636(1, 2), PIC16F639(1, 2) VDD range 2.0V to 5.5V Temperature Range: I E Package: MD MF ML P SL SN SS = = = = = = = ST = Pattern: = -40°C to +85°C = -40°C to +125°C PIC12F635-E/P 301 = Extended Temp.
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WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.