Datasheet

© 2009 Microchip Technology Inc. DS40044G-page 83
PIC16F627A/628A/648A
FIGURE 12-5: ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT
FIGURE 12-6: ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST
FIGURE 12-7: ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST FOLLOWED BY
VALID DATA BYTE
Start
bit
bit 1bit 0
bit 8 bit 0Stop
bit
Start
bit bit 8
Stop
bit
RB1/RX/DT (Pin)
RCV Buffer Reg
RCV Shift Reg
Read RCV
Buffer Reg
RCREG
RCIF
(interrupt flag)
Word 1
RCREG
bit 8 = 0, Data Byte bit 8 = 1, Address Byte
ADEN = 1
(Address Match
Enable)
‘1’ ‘1’
Note: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG
(Receive Buffer) because ADEN = 1 and bit 8 = 0.
Start
bit
bit 1bit 0
bit 8 bit 0Stop
bit
Start
bit bit 8
Stop
bit
RB1/RX/DT (pin)
RCV Buffer Reg
RCV Shift Reg
Read RCV
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
Word 1
RCREG
bit 8 = 1, Address Byte bit 8 = 0, Data Byte
ADEN = 1
(Address Match
Enable)
‘1’ ‘1’
Note: This timing diagram shows an address byte followed by an data byte. The data byte is not read into the RCREG
(receive buffer) because ADEN was not updated (still = 1) and bit 8 = 0.
Start
bit
bit 1bit 0
bit 8 bit 0Stop
bit
Start
bit bit 8
Stop
bit
RB1/RX/DT (pin)
Reg
RCV Buffer Reg
RCV Shift
Read RCV
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
Word 2
RCREG
bit 8 = 1, Address Byte bit 8 = 0, Data Byte
ADEN
(Address Match
Enable)
Word 1
RCREG
Note: This timing diagram shows an address byte followed by an data byte. The data byte is read into the RCREG
(Receive Buffer) because ADEN was updated after an address match, and was cleared to a ‘0’, so the contents
of the Receive Shift Register (RSR) are read into the Receive Buffer regardless of the value of bit 8.