Datasheet

PIC16F627A/628A/648A
DS40044G-page 60 © 2009 Microchip Technology Inc.
9.3 PWM Mode
In Pulse Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTB data latch,
the TRISB<3> bit must be cleared to make the CCP1
pin an output.
Figure 9-3 shows a simplified block diagram of the
CCP module in PWM mode.
For a step by step procedure on how to set up the CCP
module for PWM operation, see Section 9.3.3 “Set-
Up for PWM Operation”.
FIGURE 9-3: SIMPLIFIED PWM BLOCK
DIAGRAM
A PWM output (Figure 9-4) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(frequency = 1/period).
FIGURE 9-4: PWM OUTPUT
9.3.1 PWM PERIOD
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula:
PWM frequency is defined as 1/[PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
•TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
Note: Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTB I/O data
latch.
CCPR1L
CCPR1H (Slave)
Comparator
TMR2
Comparator
PR2
(1)
R
Q
S
Duty cycle registers
CCP1CON<5:4>
Clear Timer,
CCP1 pin and
latch D.C.
TRISB<3>
RB3/CCP1
Note 1: 8-bit timer is concatenated with 2-bit internal Q
clock or 2 bits of the prescaler to create 10-bit
time base.
Note: The Timer2 postscaler (see Section 8.0
“Timer2 Module”) is not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
Period
Duty Cycle
TMR2 = PR2
TMR2 = Duty Cycle
TMR2 = PR2
PWM period PR2()1+[]4 ⋅⋅= Tosc TMR2 prescale⋅
value