Datasheet

PIC16F627A/628A/648A
DS40044G-page 48 © 2009 Microchip Technology Inc.
6.3 Timer0 Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer. A prescaler assignment for the Timer0 module
means that there is no postscaler for the Watchdog
Timer, and vice-versa.
The PSA and PS<2:0> bits (OPTION<3:0>) determine
the prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF 1, MOVWF 1,
BSF 1, x....etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the Watchdog Timer. The prescaler
is not readable or writable.
FIGURE 6-1: BLOCK DIAGRAM OF THE TIMER0/WDT
T0CKI
T0SE
pin
F
OSC/4
SYNC
2
Cycles
TMR0 Reg
8-to-1MUX
Watchdog
Timer
PSA
WDT
Time-out
PS<2:0>
8
.
PSA
WDT Enable bit
Data Bus
Set flag bit T0IF
on Overflow
8
PSA
Note: T0SE, T0CS, PSA, PS<2:0> are bits in the Option Register.
T0CS
WDT Postscaler/
TMR0 Prescaler
1
0
1
0
1
0
1
0
TMR1 Clock Source