Datasheet

© 2009 Microchip Technology Inc. DS40044G-page 45
PIC16F627A/628A/648A
TABLE 5-3: PORTB FUNCTIONS
TABLE 5-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name Function Input Type
Output
Type
Description
RB0/INT RB0 TTL CMOS Bidirectional I/O port. Can be software programmed for
internal weak pull-up.
INT ST — External interrupt
RB1/RX/DT RB1 TTL CMOS Bidirectional I/O port. Can be software programmed for
internal weak pull-up.
RX ST — USART Receive Pin
DT ST CMOS Synchronous data I/O
RB2/TX/CK RB2 TTL CMOS Bidirectional I/O port
TX — CMOS USART Transmit Pin
CK ST CMOS Synchronous Clock I/O. Can be software programmed
for internal weak pull-up.
RB3/CCP1 RB3 TTL CMOS Bidirectional I/O port. Can be software programmed for
internal weak pull-up.
CCP1 ST CMOS Capture/Compare/PWM/I/O
RB4/PGM RB4 TTL CMOS Bidirectional I/O port. Interrupt-on-pin change. Can be
software programmed for internal weak pull-up.
PGM ST — Low-voltage programming input pin. When low-voltage
programming is enabled, the interrupt-on-pin change
and weak pull-up resistor are disabled.
RB5 RB5 TTL CMOS Bidirectional I/O port. Interrupt-on-pin change. Can be
software programmed for internal weak pull-up.
RB6/T1OSO/T1CKI/
PGC
RB6 TTL CMOS Bidirectional I/O port. Interrupt-on-pin change. Can be
software programmed for internal weak pull-up.
T1OSO — XTAL Timer1 Oscillator Output
T1CKI ST — Timer1 Clock Input
PGC ST — ICSP
™
Programming Clock
RB7/T1OSI/PGD RB7 TTL CMOS Bidirectional I/O port. Interrupt-on-pin change. Can be
software programmed for internal weak pull-up.
T1OSI XTAL — Timer1 Oscillator Input
PGD ST CMOS ICSP Data I/O
Legend: O = Output CMOS = CMOS Output P = Power
— = Not used I = Input ST = Schmitt Trigger Input
TTL = TTL Input OD = Open Drain Output AN = Analog
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR
Value on
All Other
Resets
06h, 106h PORTB RB7 RB6 RB5 RB4
(1)
RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu
86h, 186h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
81h, 181h OPTION RBPU
INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: u = unchanged, x = unknown. Shaded cells are not used for PORTB.
Note 1: LVP configuration bit sets RB4 functionality.