Datasheet

© 2009 Microchip Technology Inc. DS40044G-page 39
PIC16F627A/628A/648A
FIGURE 5-9: BLOCK DIAGRAM OF
RB1/RX/DT PIN
FIGURE 5-10: BLOCK DIAGRAM OF
RB2/TX/CK PIN
Data Latch
TRIS Latch
RD TRISB
Q
D
Q
CK
Q
D
Q
CK
1
0
WR PORTB
WR TRISB
Schmitt
Trigger
Peripheral OE
(1)
Data Bus
SPEN
USART Data Output
USART Receive Input
RBPU
VDD
P
EN
QD
VDD
VSS
Note 1: Peripheral OE (output enable) is only active if
peripheral select is active.
RD PORTB
RX/DT
RB1/
TTL
Input
Buffer
Weak
Pull-up
Data Latch
TRIS Latch
RD TRISB
Q
D
Q
CK
Q
D
Q
CK
1
0
WR PORTB
WR TRISB
Schmitt
Trigger
Peripheral OE
(1)
Data Bus
SPEN
USART TX/CK Output
USART Slave Clock In
RBPU
VDD
P
EN
QD
VDD
VSS
Note 1: Peripheral OE (output enable) is only active if
peripheral select is active.
RD PORTB
TTL
Input
Buffer
RB2/
TX/CK
Weak
Pull-up