Datasheet

© 2009 Microchip Technology Inc. DS40044G-page 35
PIC16F627A/628A/648A
FIGURE 5-4: BLOCK DIAGRAM OF RA4/T0CKI/CMP2 PIN
FIGURE 5-5: BLOCK DIAGRAM OF THE
RA5/MCLR
/VPP PIN
FIGURE 5-6: BLOCK DIAGRAM OF
RA6/OSC2/CLKOUT PIN
Data
Bus
QD
Q
CK
N
WR
PORTA
WR
TRISA
Data Latch
TRIS Latch
RD TRISA
RD PORTA
Vss
RA4 Pin
QD
Q
CK
DQ
EN
TMR0 Clock Input
Schmitt Trigger
Input Buffer
Comparator Output
Comparator Mode = 110
Vss
1
0
(CMCON Reg.)
D
Q
EN
HV Detect
MCLR
Filter
RA5/MCLR/VPP
MCLR
Program
MCLRE
RD
VSS
Data
Bus
VSS
PORTA
RD
circuit
mode
Schmitt Trigger
Input Buffer
TRISA
(Configuration Bit)
WR
D
CK
Q
Q
PORTA
WR
TRISA
VDD
VSS
CLKOUT(FOSC/4)
FOSC =
101, 111
(2)
QD
RD
EN
RD PORTA
F
OSC =
D
CK
Q
Q
011, 100, 110
(1)
TRISA
From OSC1
OSC
Circuit
Note 1: INTOSC with RA6 = I/O or RC with RA6 = I/O.
2: INTOSC with RA6 = CLKOUT or RC with
RA6 = CLKOUT.
Schmitt
Trigger
Input Buffer
Data Latch
TRIS Latch
1
0