Datasheet
© 2009 Microchip Technology Inc. DS40044G-page 21
PIC16F627A/628A/648A
TABLE 4-4: SPECIAL FUNCTION REGISTERS SUMMARY BANK1
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR
Reset
(1)
Details
on Page
Bank 1
80h INDF Addressing this location uses contents of FSR to address data memory (not a physical
register)
xxxx xxxx 30
81h OPTION RBPU
INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 25
82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 30
83h STATUS IRP RP1 RP0 TO
PD ZDCC0001 1xxx 24
84h FSR Indirect Data Memory Address Pointer xxxx xxxx 30
85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 33
86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 38
87h — Unimplemented — —
88h — Unimplemented — —
89h — Unimplemented — —
8Ah PCLATH
— — — Write Buffer for upper 5 bits of Program Counter ---0 0000 30
8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 26
8Ch PIE1 EEIE CMIE RCIE TXIE
— CCP1IE TMR2IE TMR1IE 0000 -000 27
8Dh — Unimplemented — —
8Eh PCON
— — — — OSCF —PORBOR ---- 1-0x 29
8Fh — Unimplemented — —
90h — Unimplemented — —
91h — Unimplemented — —
92h PR2 Timer2 Period Register 1111 1111 54
93h — Unimplemented — —
94h — Unimplemented — —
95h — Unimplemented — —
96h — Unimplemented — —
97h — Unimplemented — —
98h TXSTA CSRC TX9 TXEN SYNC
— BRGH TRMT TX9D 0000 -010 73
99h SPBRG Baud Rate Generator Register 0000 0000 75
9Ah EEDATA EEPROM Data Register xxxx xxxx 91
9Bh EEADR EEPROM Address Register xxxx xxxx 92
9Ch EECON1
— — — — WRERR WREN WR RD ---- x000 92
9Dh EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- 92
9Eh — Unimplemented — —
9Fh VRCON VREN VROE VRR
— VR3 VR2 VR1 VR0 000- 0000 69
Legend: - = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: For the initialization condition for registers tables, refer to Table 14-6 and Table 14-7.