Datasheet
PIC16F627A/628A/648A
DS40044G-page 20 © 2009 Microchip Technology Inc.
4.2.2 SPECIAL FUNCTION REGISTERS
The SFRs are registers used by the CPU and Periph-
eral functions for controlling the desired operation of
the device (Table 4-3). These registers are static RAM.
The special registers can be classified into two sets
(core and peripheral). The SFRs associated with the
“core” functions are described in this section. Those
related to the operation of the peripheral features are
described in the section of that peripheral feature.
TABLE 4-3: SPECIAL REGISTERS SUMMARY BANK0
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR
Reset
(1)
Details
on Page
Bank 0
00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 30
01h TMR0 Timer0 Module’s Register xxxx xxxx 47
02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 30
03h STATUS IRP RP1 RP0 TO
PD ZDC C0001 1xxx 24
04h FSR Indirect Data Memory Address Pointer xxxx xxxx 30
05h PORTA
RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx 0000 33
06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 38
07h — Unimplemented — —
08h — Unimplemented — —
09h — Unimplemented — —
0Ah PCLATH — — — Write Buffer for upper 5 bits of Program Counter ---0 0000 30
0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 26
0Ch PIR1
EEIF CMIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 28
0Dh — Unimplemented — —
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx 50
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx 50
10h T1CON
— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 50
11h TMR2 TMR2 Module’s Register 0000 0000 54
12h T2CON
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 54
13h — Unimplemented — —
14h — Unimplemented — —
15h CCPR1L Capture/Compare/PWM Register (LSB) xxxx xxxx 57
16h CCPR1H Capture/Compare/PWM Register (MSB) xxxx xxxx 57
17h CCP1CON
— — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 57
18h RCSTA SPEN RX9 SREN CREN ADEN FERR OERR RX9D 0000 000x 74
19h TXREG USART Transmit Data Register 0000 0000 79
1Ah RCREG USART Receive Data Register 0000 0000 82
1Bh — Unimplemented — —
1Ch — Unimplemented — —
1Dh — Unimplemented — —
1Eh — Unimplemented — —
1Fh CMCON C2OUT C1OUT
C2INV C1INV CIS CM2 CM1 CM0 0000 0000 63
Legend: - = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: For the initialization condition for registers tables, refer to Table 14-6 and Table 14-7.