Datasheet

© 2009 Microchip Technology Inc. DS40044G-page 147
PIC16F627A/628A/648A
FIGURE 17-7: BROWN-OUT RESET TIMING
TABLE 17-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER REQUIREMENTS
FIGURE 17-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
Parameter
No.
Sym Characteristic Min Typ† Max Units Conditions
30 TMCLMCLR Pulse Width (low) 2000 — — ns VDD = 5V, -40°C to +85°C
31 T
WDT Watchdog Timer Time out Period
(No Prescaler)
7* 18 33* ms VDD = 5V, -40°C to +85°C
32 T
OST Oscillation Start-up Timer Period — 1024 TOSC ——TOSC = OSC1 period
33 T
PWRT Power-up Timer Period 28* 72 132* ms VDD = 5V, -40°C to +85°C
34 T
IOZ I/O High-impedance from MCLR
Low or Watchdog Timer Reset
— — 2.0* μs
35 T
BOR Brown-out Reset pulse width 100* — — μsVDD ≤ VBOR (D005)
Legend: TBD = To Be Determined.
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
VDD
VBOR
35
46
47
45
48
41
42
40
RA4/T0CKI/CMP2
RB6/T1OSO/T1CKI/PGC
TMR0 OR
TMR1