Datasheet

PIC16F627A/628A/648A
DS40044G-page 146 © 2009 Microchip Technology Inc.
TABLE 17-6: CLKOUT AND I/O TIMING REQUIREMENTS
FIGURE 17-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
Parameter
No.
Sym Characteristic Min Typ† Max Units
10 T
OSH2CKLOSC1↑ to CLKOUT↓
PIC16F62XA
—75200*ns
10A PIC16LF62XA — — 400* ns
11 T
OSH2CKHOSC1↑ to CLKOUT↑ PIC16F62XA — 75 200* ns
11A PIC16LF62XA — — 400* ns
12 TCKR CLKOUT rise time PIC16F62XA — 35 100* ns
12A PIC16LF62XA — — 200* ns
13 T
CKF CLKOUT fall time PIC16F62XA — 35 100* ns
13A PIC16LF62XA — — 200* ns
14 T
CKL2IOVCLKOUT ↓ to Port out valid — — 20* ns
15 TIOV2CKH Port in valid before CLKOUT ↑ PIC16F62XA TOSC+200 ns* — — ns
PIC16LF62XA TOSC+400 ns* — — ns
16 T
CKH2IOI Port in hold after CLKOUT ↑ 0 — — ns
17 T
OSH2IOVOSC1↑ (Q1 cycle) to PIC16F62XA — 50 150* ns
Port out valid PIC16LF62XA — — 300* ns
18 T
OSH2IOIOSC1↑ (Q2 cycle) to Port input invalid
(I/O in hold time)
100*
200*
——ns
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
VDD
MCLR
Internal
POR
PWRT
Time out
OST
Time out
Internal
Reset
Watchdog
Timer
Reset
33
32
30
31
34
I/O Pins
34