Datasheet

© 2009 Microchip Technology Inc. DS40044G-page 129
PIC16F627A/628A/648A
SUBWF Subtract W from f
Syntax: [ label ] SUBWF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) - (W) → (dest)
Status
Affected:
C, DC, Z
Encoding:
00 0010 dfff ffff
Description: Subtract (2’s complement method)
W register from register ‘f’. If ‘d’ is
‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
Words: 1
Cycles: 1
Example 1
:
SUBWF REG1, 1
Before Instruction
REG1 = 3
W=2
C=?
After Instruction
REG1 = 1
W=2
C=1; result is positive
DC = 1
Z=0
Example 2
: Before Instruction
REG1 = 2
W=2
C=?
After Instruction
REG1 = 0
W=2
C=1; result is zero
Z = DC = 1
Example 3
: Before Instruction
REG1 = 1
W=2
C=?
After Instruction
REG1 = 0xFF
W=2
C=0; result is negative
Z = DC = 0
SWAPF Swap Nibbles in f
Syntax: [ label ] SWAPF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f<3:0>) → (dest<7:4>),
(f<7:4>) → (dest<3:0>)
Status Affected: None
Encoding:
00 1110 dfff ffff
Description: The upper and lower nibbles of
register ‘f’ are exchanged. If ‘d’ is
‘0’, the result is placed in W
register. If ‘d’ is ‘1’, the result is
placed in register ‘f’.
Words: 1
Cycles: 1
Example
SWAPF REG1, 0
Before Instruction
REG1 = 0xA5
After Instruction
REG1 = 0xA5
W=0x5A
TRIS Load TRIS Register
Syntax: [ label ] TRIS f
Operands: 5 ≤ f ≤ 7
Operation: (W) → TRIS register f;
Status Affected: None
Encoding:
00 0000 0110 0fff
Description: The instruction is supported for
code compatibility with the
PIC16C5X products. Since TRIS
registers are readable and
writable, the user can directly
address them.
Words: 1
Cycles: 1
Example
To maintain upward compatibil-
ity with future PIC
®
MCU
products, do not use this
instruction.