Datasheet

PIC16F627A/628A/648A
DS40044G-page 122 © 2009 Microchip Technology Inc.
CLRW Clear W
Syntax: [ label ] CLRW
Operands: None
Operation: 00h → (W)
1 → Z
Status Affected: Z
Encoding:
00 0001 0000 0011
Description: W register is cleared. Zero bit
(Z) is set.
Words: 1
Cycles: 1
Example
CLRW
Before Instruction
W = 0x5A
After Instruction
W = 0x00
Z=1
CLRWDT Clear Watchdog Timer
Syntax: [ label ] CLRWDT
Operands: None
Operation: 00h → WDT
0 → WDT prescaler,
1 → TO
1 → PD
Status Affected: TO, PD
Encoding:
00 0000 0110 0100
Description: CLRWDT instruction resets the
Watchdog Timer. It also resets
the prescaler of the WDT. Status
bits TO
and PD are set.
Words: 1
Cycles: 1
Example
CLRWDT
Before Instruction
WDT counter = ?
After Instruction
WDT counter = 0x00
WDT prescaler = 0
TO
= 1
PD
= 1
COMF Complement f
Syntax: [ label ] COMF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f
) → (dest)
Status Affected: Z
Encoding:
00 1001 dfff ffff
Description: The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’,
the result is stored back in
register ‘f’.
Words: 1
Cycles: 1
Example
COMF REG1, 0
Before Instruction
REG1 = 0x13
After Instruction
REG1 = 0x13
W=0xEC
DECF Decrement f
Syntax: [ label ] DECF f,d
Operands: 0 ≤ f ≤ 127
d ∈ [0,1]
Operation: (f) - 1 → (dest)
Status Affected: Z
Encoding:
00 0011 dfff ffff
Description: Decrement register ‘f’. If ‘d’ is
‘0’. the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
Words: 1
Cycles: 1
Example
DECF CNT, 1
Before Instruction
CNT = 0x01
Z=0
After Instruction
CNT = 0x00
Z=1