Datasheet

PIC16F627A/628A/648A
DS40044G-page 12 © 2009 Microchip Technology Inc.
FIGURE 3-1: BLOCK DIAGRAM
Note 1: Higher order bits are from the Status register.
Flash
Program
Memory
13
Data Bus
8
14
Program
Bus
Instruction Reg
Program Counter
8-Level Stack
(13-bit)
RAM
File
Registers
Direct Addr
7
RAM Addr (1)
9
Addr MUX
Indirect
Addr
FSR Reg
Status Reg
MUX
ALU
W Reg
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
MCLR
VDD, VSS
PORTA
PORTB
RA4/T0CK1/CMP2
RA5/MCLR
/VPP
RB0/INT
8
8
Brown-out
Reset
USART
CCP1
Timer0 Timer1 Timer2
RA3/AN3/CMP1
RA2/AN2/VREF
RA1/AN1
RA0/AN0
8
3
RB1/RX/DT
RB2/TX/CK
RB3/CCP1
RB4/PGM
RB5
RB6/T1OSO/T1CKI/PGC
RB7/T1OSI/PGD
Low-Voltage
Programming
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
VREF
Comparator
Data EEPROM