Datasheet

PIC16F627A/628A/648A
DS40044G-page 110 © 2009 Microchip Technology Inc.
14.5.1 RB0/INT INTERRUPT
External interrupt on the RB0/INT pin is edge triggered;
either rising if INTEDG bit (OPTION<6>) is set, or
falling, if INTEDG bit is clear. When a valid edge
appears on the RB0/INT pin, the INTF bit
(INTCON<1>) is set. This interrupt can be disabled by
clearing the INTE control bit (INTCON<4>). The INTF
bit must be cleared in software in the interrupt service
routine before re-enabling this interrupt. The RB0/INT
interrupt can wake-up the processor from Sleep, if the
INTE bit was set prior to going into Sleep. The status of
the GIE bit decides whether or not the processor
branches to the interrupt vector following wake-up. See
Section 14.8 “Power-Down Mode (Sleep)” for details
on Sleep, and Figure 14-17 for timing of wake-up from
Sleep through RB0/INT interrupt.
14.5.2 TMR0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will set the
T0IF (INTCON<2>) bit. The interrupt can be enabled/
disabled by setting/clearing T0IE (INTCON<5>) bit. For
operation of the Timer0 module, see Section 6.0
“Timer0 Module”.
14.5.3 PORTB INTERRUPT
An input change on PORTB <7:4> sets the RBIF
(INTCON<0>) bit. The interrupt can be enabled/disabled
by setting/clearing the RBIE (INTCON<3>) bit. For
operation of PORTB (Section 5.2 “PORTB and TRISB
Registers”).
14.5.4 COMPARATOR INTERRUPT
See Section 10.6 “Comparator Interrupts” for
complete description of comparator interrupts.
FIGURE 14-15: INT PIN INTERRUPT TIMING
Note: If a change on the I/O pin should occur
when the read operation is being executed
(starts during the Q2 cycle and ends before
the start of the Q3 cycle), then the RBIF
interrupt flag may not get set.
Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4
OSC1
CLKOUT
INT pin
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
Instruction Flow
PC
Instruction
Fetched
Instruction
Executed
Interrupt Latency
PC
PC + 1
PC + 1
0004h
0005h
Inst (0004h)
Inst (0005h)
Dummy Cycle
Inst (PC)
Inst (PC + 1)
Inst (PC - 1)
Inst (0004h)
Dummy Cycle
Inst (PC)
—
Note 1: INTF flag is sampled here (every Q1).
2: Asynchronous interrupt latency = 3-4 T
CY. Synchronous latency = 3 TCY, where TCY = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a two-cycle instruction.
3: CLKOUT is available in RC and INTOSC oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF is enabled to be set anytime during the Q4-Q1 cycles.
(1)
(1)
(4)
(5)
(2)
(3)