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PIC16F627A/628A/648A

Data Sheet

Flash-Based, 8-Bit CMOS

Microcontrollers with nanoWatt Technology

Summary of content (180 pages)

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PIC16F627A/628A/648A Data Sheet Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology © 2009 Microchip Technology Inc.
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Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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PIC16F627A/628A/648A 18-pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology High-Performance RISC CPU: Low-Power Features: • • • • • • Standby Current: - 100 nA @ 2.0V, typical • Operating Current: - 12 μA @ 32 kHz, 2.0V, typical - 120 μA @ 1 MHz, 2.0V, typical • Watchdog Timer Current: - 1 μA @ 2.0V, typical • Timer1 Oscillator Current: - 1.2 μA @ 32 kHz, 2.0V, typical • Dual-speed Internal Oscillator: - Run-time selectable between 4 MHz and 48 kHz - 4 μs wake-up from Sleep, 3.
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PIC16F627A/628A/648A Pin Diagrams PDIP, SOIC 1 18 RA1/AN1 RA3/AN3/CMP1 2 17 RA0/AN0 16 RA7/OSC1/CLKIN 15 RA6/OSC2/CLKOUT 14 VDD 13 RB7/T1OSI/PGD 12 RB6/T1OSO/T1CKI/PGC 11 RB5 10 RB4/PGM 3 RA5/MCLR/VPP 4 RB0/INT 6 RB1/RX/DT 7 RB2/TX/CK 8 RB3/CCP1 9 RA5/MCLR/VPP DS40044G-page 4 RA1/AN1 RA0/AN0 8 9 10 NC 11 12 RB4/PGM 13 RB5 NC 14 1 21 NC 2 20 VSS 3 19 NC 4 PIC16F627A/628A 18 NC PIC16F648A VSS 17 5 NC 6 16 RB0/INT 7 15 RA7/OSC1/CLKIN RA6/OSC2/CLKOUT VDD VDD RB7/T1OSI/PGD R
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PIC16F627A/628A/648A Table of Contents 1.0 General Description ........................................................................................................................................................................ 7 2.0 PIC16F627A/628A/648A Device Varieties...................................................................................................................................... 9 3.0 Architectural Overview .........................................................................
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PIC16F627A/628A/648A 1.0 GENERAL DESCRIPTION The PIC16F627A/628A/648A are 18-pin Flash-based members of the versatile PIC16F627A/628A/648A family of low-cost, high-performance, CMOS, fullystatic, 8-bit microcontrollers. All PIC® microcontrollers employ an advanced RISC architecture. The PIC16F627A/628A/648A have enhanced core features, an eight-level deep stack, and multiple internal and external interrupt sources.
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PIC16F627A/628A/648A 2.0 PIC16F627A/628A/648A DEVICE VARIETIES A variety of frequency ranges and packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in the PIC16F627A/628A/648A Product Identification System, at the end of this data sheet. When placing orders, please use this page of the data sheet to specify the correct part number. 2.
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PIC16F627A/628A/648A 3.0 ARCHITECTURAL OVERVIEW The high performance of the PIC16F627A/628A/648A family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16F627A/628A/648A uses a Harvard architecture in which program and data are accessed from separate memories using separate busses. This improves bandwidth over traditional Von Neumann architecture where program and data are fetched from the same memory.
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PIC16F627A/628A/648A FIGURE 3-1: BLOCK DIAGRAM 13 Flash Program Memory RAM File Registers 8-Level Stack (13-bit) Program Bus 14 8 Data Bus Program Counter RAM Addr (1) PORTA 9 Addr MUX Instruction Reg Direct Addr 7 8 RA0/AN0 RA1/AN1 RA2/AN2/VREF RA3/AN3/CMP1 RA4/T0CK1/CMP2 RA5/MCLR/VPP RA6/OSC2/CLKOUT RA7/OSC1/CLKIN Indirect Addr FSR Reg Status Reg 8 3 Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT Oscillator Start-up Timer Power-on Reset Watchdog Ti
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PIC16F627A/628A/648A TABLE 3-2: PIC16F627A/628A/648A PINOUT DESCRIPTION Name Function RA0/AN0 RA1/AN1 RA2/AN2/VREF RA3/AN3/CMP1 RA4/T0CKI/CMP2 RA5/MCLR/VPP Input Type Output Type CMOS Description RA0 ST Bidirectional I/O port AN0 AN — RA1 ST CMOS AN1 AN — RA2 ST CMOS AN2 AN — Analog comparator input VREF — AN VREF output RA3 ST CMOS AN3 AN — CMP1 — CMOS Comparator 1 output RA4 ST OD Bidirectional I/O port T0CKI ST — Timer0 clock input CMP2 — OD Comparato
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PIC16F627A/628A/648A TABLE 3-2: PIC16F627A/628A/648A PINOUT DESCRIPTION (CONTINUED) Name RB4/PGM Function Input Type Output Type Description RB4 TTL CMOS Bidirectional I/O port. Interrupt-on-pin change. Can be software programmed for internal weak pull-up. PGM ST — RB5 RB5 TTL CMOS Bidirectional I/O port. Interrupt-on-pin change. Can be software programmed for internal weak pull-up. RB6/T1OSO/T1CKI/PGC RB6 TTL CMOS Bidirectional I/O port. Interrupt-on-pin change.
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PIC16F627A/628A/648A 3.1 Clocking Scheme/Instruction Cycle 3.2 Instruction Flow/Pipelining An instruction cycle consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g.
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PIC16F627A/628A/648A 4.0 MEMORY ORGANIZATION 4.1 Program Memory Organization The PIC16F627A/628A/648A has a 13-bit program counter capable of addressing an 8K x 14 program memory space. Only the first 1K x 14 (0000h-03FFh) for the PIC16F627A, 2K x 14 (0000h-07FFh) for the PIC16F628A and 4K x 14 (0000h-0FFFh) for the PIC16F648A are physically implemented.
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PIC16F627A/628A/648A FIGURE 4-2: DATA MEMORY MAP OF THE PIC16F627A AND PIC16F628A File Address Indirect addr.(1) 00h Indirect addr.(1) 80h Indirect addr.(1) 100h Indirect addr.
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PIC16F627A/628A/648A FIGURE 4-3: DATA MEMORY MAP OF THE PIC16F648A File Address Indirect addr.(1) 00h Indirect addr.(1) 80h Indirect addr.(1) 100h Indirect addr.
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PIC16F627A/628A/648A 4.2.2 SPECIAL FUNCTION REGISTERS The SFRs are registers used by the CPU and Peripheral functions for controlling the desired operation of the device (Table 4-3). These registers are static RAM. The special registers can be classified into two sets (core and peripheral). The SFRs associated with the “core” functions are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature.
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PIC16F627A/628A/648A TABLE 4-4: Address SPECIAL FUNCTION REGISTERS SUMMARY BANK1 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset(1) Details on Page xxxx xxxx 30 1111 1111 25 0000 0000 30 0001 1xxx 24 xxxx xxxx 30 Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 81h OPTION 82h PCL 83h STATUS 84h FSR 85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 33 86
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PIC16F627A/628A/648A TABLE 4-5: Address SPECIAL FUNCTION REGISTERS SUMMARY BANK2 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset(1) Details on Page Bank 2 100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 30 101h TMR0 Timer0 Module’s Register xxxx xxxx 47 102h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 30 103h STATUS 0001 1xxx 24 104h FSR xxxx xxxx 30 IRP RP1 RP0 TO
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PIC16F627A/628A/648A TABLE 4-6: Address SPECIAL FUNCTION REGISTERS SUMMARY BANK3 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset(1) Details on Page Bank 3 180h INDF 181h OPTION 182h PCL 183h STATUS 184h FSR Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Program Counter’s (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C Indirect Data Memory Address
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PIC16F627A/628A/648A 4.2.2.1 Status Register The Status register, shown in Register 4-1, contains the arithmetic status of the ALU; the Reset status and the bank select bits for data memory (SRAM). The Status register can be the destination for any instruction, like any other register. If the Status register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic.
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PIC16F627A/628A/648A 4.2.2.2 OPTION Register Note: The Option register is a readable and writable register, which contains various control bits to configure the TMR0/WDT prescaler, the external RB0/INT interrupt, TMR0 and the weak pull-ups on PORTB. REGISTER 4-2: To achieve a 1:1 prescaler assignment for TMR0, assign the prescaler to the WDT (PSA = 1). See Section 6.3.1 “Switching Prescaler Assignment”.
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PIC16F627A/628A/648A 4.2.2.3 INTCON Register Note: The INTCON register is a readable and writable register, which contains the various enable and flag bits for all interrupt sources except the comparator module. See Section 4.2.2.4 “PIE1 Register” and Section 4.2.2.5 “PIR1 Register” for a description of the comparator enable and flag bits.
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PIC16F627A/628A/648A 4.2.2.4 PIE1 Register This register contains interrupt enable bits.
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PIC16F627A/628A/648A 4.2.2.5 PIR1 Register Note: This register contains interrupt flag bits. REGISTER 4-5: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
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PIC16F627A/628A/648A 4.2.2.6 PCON Register The PCON register contains flag bits to differentiate between a Power-on Reset, an external MCLR Reset, WDT Reset or a Brown-out Reset. REGISTER 4-6: Note: BOR is unknown on Power-on Reset. It must then be set by the user and checked on subsequent Resets to see if BOR is cleared, indicating a brown-out has occurred.
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PIC16F627A/628A/648A 4.3 PCL and PCLATH The Program Counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 4-4 shows the two situations for loading the PC. The upper example in Figure 4-4 shows how the PC is loaded on a write to PCL (PCLATH<4:0> → PCH).
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PIC16F627A/628A/648A FIGURE 4-5: Status Register RP1 RP0 DIRECT/INDIRECT ADDRESSING PIC16F627A/628A/648A Status Register IRP Direct Addressing 6 from opcode bank select 0 location select 00 00h Indirect Addressing 7 bank select 01 10 FSR Register 0 location select 11 180h RAM File Registers 7Fh 1FFh Bank 0 Note: Bank 1 Bank 2 Bank 3 For memory map detail see Figure 4-3, Figure 4-2 and Figure 4-1. © 2009 Microchip Technology Inc.
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PIC16F627A/628A/648A 5.0 I/O PORTS The PIC16F627A/628A/648A have two ports, PORTA and PORTB. Some pins for these I/O ports are multiplexed with alternate functions for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. 5.1 PORTA and TRISA Registers PORTA is an 8-bit wide latch. RA4 is a Schmitt Trigger input and an open drain output. Port RA4 is multiplexed with the T0CKI clock input.
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PIC16F627A/628A/648A FIGURE 5-2: Data Bus BLOCK DIAGRAM OF RA2/AN2/VREF PIN D WR PORTA Q CK VDD Q Data Latch D WR TRISA Q CK RA2 Pin Analog Input Mode (CMCON Reg.) Q TRIS Latch RD TRISA VSS Schmitt Trigger Input Buffer Q D EN RD PORTA To Comparator VROE VREF FIGURE 5-3: Data Bus BLOCK DIAGRAM OF THE RA3/AN3/CMP1 PIN Comparator Mode = 110 (CMCON Reg.) D Comparator Output WR PORTA 1 CK Q Data Latch D WR TRISA VDD Q 0 Q CK RA3 Pin Analog Input Mode (CMCON Reg.
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PIC16F627A/628A/648A FIGURE 5-4: Data Bus BLOCK DIAGRAM OF RA4/T0CKI/CMP2 PIN Comparator Mode = 110 D (CMCON Reg.
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PIC16F627A/628A/648A FIGURE 5-7: BLOCK DIAGRAM OF RA7/OSC1/CLKIN PIN To Clock Circuits Data Bus D WR PORTA VDD Q RA7/OSC1/CLKIN Pin CK Q Data Latch D WR TRISA CK VSS Q Q TRIS Latch RD TRISA FOSC = 100, 101(1) Q D EN Schmitt Trigger Input Buffer RD PORTA Note 1: DS40044G-page 36 INTOSC with CLKOUT and INTOSC with I/O. © 2009 Microchip Technology Inc.
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PIC16F627A/628A/648A TABLE 5-1: PORTA FUNCTIONS Name RA0/AN0 RA1/AN1 RA2/AN2/VREF RA3/AN3/CMP1 RA4/T0CKI/CMP2 RA5/MCLR/VPP RA6/OSC2/CLKOUT RA7/OSC1/CLKIN Legend: Function Input Type Output Type RA0 ST CMOS AN0 AN — RA1 ST CMOS AN1 AN — RA2 ST CMOS AN2 AN — Analog comparator input VREF — AN VREF output RA3 ST CMOS AN3 AN — CMP1 — CMOS RA4 ST OD Bidirectional I/O port. Output is open drain type.
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PIC16F627A/628A/648A 5.2 PORTB and TRISB Registers PORTB is an 8-bit wide bidirectional port. The corresponding data direction register is TRISB. A ‘1’ in the TRISB register puts the corresponding output driver in a High-impedance mode. A ‘0’ in the TRISB register puts the contents of the output latch on the selected pin(s). PORTB is multiplexed with the external interrupt, USART, CCP module and the TMR1 clock input/output.
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PIC16F627A/628A/648A FIGURE 5-9: BLOCK DIAGRAM OF RB1/RX/DT PIN FIGURE 5-10: BLOCK DIAGRAM OF RB2/TX/CK PIN VDD RBPU Weak P Pull-up VDD SPEN USART Data Output Data Bus WR PORTB Q CK Q RB1/ RX/DT 0 WR TRISB Q CK Q Data Bus WR PORTB Data Latch D SPEN USART TX/CK Output 1 D VDD Weak P Pull-up VDD RBPU 1 D Q CK Q Data Latch VSS WR TRISB TRIS Latch D Q CK Q VSS TRIS Latch Peripheral OE(1) Peripheral OE(1) TTL Input Buffer RD TRISB Q TTL Input Buffer RD TRISB D Q EN RD
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PIC16F627A/628A/648A FIGURE 5-11: BLOCK DIAGRAM OF RB3/CCP1 PIN VDD Weak P Pull-up VDD RBPU CCP1CON CCP output 0 Data Bus WR PORTB D Q CK Q RB3/ CCP1 1 Data Latch WR TRISB D Q CK Q VSS TRIS Latch Peripheral OE(2) TTL Input Buffer RD TRISB Q D EN RD PORTB CCP In Schmitt Trigger Note 1: Peripheral OE (output enable) is only active if peripheral select is active. DS40044G-page 40 © 2009 Microchip Technology Inc.
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PIC16F627A/628A/648A FIGURE 5-12: BLOCK DIAGRAM OF RB4/PGM PIN VDD RBPU P weak pull-up Data Bus WR PORTB D Q CK Q VDD Data Latch WR TRISB D Q CK Q RB4/PGM VSS TRIS Latch RD TRISB LVP (Configuration Bit) RD PORTB PGM input TTL input buffer Schmitt Trigger Q D EN Q1 Set RBIF From other RB<7:4> pins Q D EN Note: Q3 The low-voltage programming disables the interrupt-on-change and the weak pull-ups on RB4. © 2009 Microchip Technology Inc.
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PIC16F627A/628A/648A FIGURE 5-13: BLOCK DIAGRAM OF RB5 PIN VDD RBPU weak VDD P pull-up Data Bus D Q CK Q RB5 pin WR PORTB Data Latch VSS WR TRISB D Q CK Q TRIS Latch TTL input buffer RD TRISB Q D RD PORTB EN Q1 Set RBIF From other RB<7:4> pins Q D EN DS40044G-page 42 Q3 © 2009 Microchip Technology Inc.
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PIC16F627A/628A/648A FIGURE 5-14: BLOCK DIAGRAM OF RB6/T1OSO/T1CKI/PGC PIN VDD RBPU P weak pull-up Data Bus WR PORTB D Q CK Q VDD Data Latch WR TRISB D Q CK Q RB6/ T1OSO/ T1CKI/ PGC pin VSS TRIS Latch RD TRISB T1OSCEN TTL input buffer RD PORTB TMR1 Clock From RB7 Schmitt Trigger TMR1 oscillator Serial Programming Clock Q D EN Q1 Set RBIF From other RB<7:4> pins Q D EN © 2009 Microchip Technology Inc.
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PIC16F627A/628A/648A FIGURE 5-15: BLOCK DIAGRAM OF THE RB7/T1OSI/PGD PIN VDD RBPU P weak pull-up TMR1 oscillator To RB6 VDD Data Bus WR PORTB D Q CK Q RB7/T1OSI/ PGD pin Data Latch WR TRISB D Q CK Q VSS TRIS Latch RD TRISB T10SCEN TTL input buffer RD PORTB Serial Programming Input Schmitt Trigger Q D EN Q1 Set RBIF From other RB<7:4> pins Q D EN DS40044G-page 44 Q3 © 2009 Microchip Technology Inc.
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PIC16F627A/628A/648A TABLE 5-3: PORTB FUNCTIONS Name Function Input Type RB0/INT RB1/RX/DT Output Type RB0 TTL CMOS INT ST — RB1 TTL CMOS Description Bidirectional I/O port. Can be software programmed for internal weak pull-up. External interrupt Bidirectional I/O port. Can be software programmed for internal weak pull-up. RX ST — DT ST CMOS RB2 TTL CMOS Bidirectional I/O port TX — CMOS USART Transmit Pin CK ST CMOS Synchronous Clock I/O.
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PIC16F627A/628A/648A 5.3 I/O Programming Considerations 5.3.1 EXAMPLE 5-2: BIDIRECTIONAL I/O PORTS Any instruction that writes operates internally as a read followed by a write operation. The BCF and BSF instructions, for example, read the register into the CPU, execute the bit operation and write the result back to the register. Caution must be used when these instructions are applied to a port with both inputs and outputs defined.
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PIC16F627A/628A/648A 6.0 TIMER0 MODULE The Timer0 module timer/counter has the following features: • • • • • • 8-bit timer/counter Read/write capabilities 8-bit software programmable prescaler Internal or external clock select Interrupt on overflow from FFh to 00h Edge select for external clock Figure 6-1 is a simplified block diagram of the Timer0 module. Additional information is available in the “PIC® Mid-Range MCU Family Reference Manual” (DS33023).
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PIC16F627A/628A/648A 6.3 The PSA and PS<2:0> bits (OPTION<3:0>) determine the prescaler assignment and prescale ratio. Timer0 Prescaler An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer. A prescaler assignment for the Timer0 module means that there is no postscaler for the Watchdog Timer, and vice-versa. FIGURE 6-1: When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF 1, MOVWF 1, BSF 1, x....etc.
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PIC16F627A/628A/648A 6.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control (i.e., it can be changed “on-the-fly” during program execution). Use the instruction sequences shown in Example 6-1 when changing the prescaler assignment from Timer0 to WDT, to avoid an unintended device Reset.
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PIC16F627A/628A/648A 7.0 TIMER1 MODULE The Timer1 module is a 16-bit timer/counter consisting of two 8-bit registers (TMR1H and TMR1L) which are readable and writable. The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The Timer1 Interrupt, if enabled, is generated on overflow of the TMR1 register pair which latches the interrupt flag bit TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing the Timer1 interrupt enable bit TMR1IE (PIE1<0>).
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PIC16F627A/628A/648A 7.1 7.2.1 Timer1 Operation in Timer Mode Timer mode is selected by clearing the TMR1CS (T1CON<1>) bit. In this mode, the input clock to the timer is FOSC/4. The synchronize control bit T1SYNC (T1CON<2>) has no effect since the internal clock is always in sync. 7.2 Timer1 Operation in Synchronized Counter Mode Counter mode is selected by setting bit TMR1CS.
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PIC16F627A/628A/648A 7.3 Timer1 Operation in Asynchronous Counter Mode If control bit T1SYNC (T1CON<2>) is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during Sleep and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (Section 7.3.2 “Reading and Writing Timer1 in Asynchronous Counter Mode”).
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PIC16F627A/628A/648A 7.4 Timer1 Oscillator 7.5 A crystal oscillator circuit is built in between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting control bit T1OSCEN (T1CON<3>). It will continue to run during Sleep. It is primarily intended for a 32.768 kHz watch crystal. Table 7-1 shows the capacitor selection for the Timer1 oscillator. If the CCP1 module is configured in Compare mode to generate a “special event trigger” (CCP1M<3:0> = 1011), this signal will reset Timer1.
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PIC16F627A/628A/648A 8.0 TIMER2 MODULE Timer2 is an 8-bit timer with a prescaler and a postscaler. It can be used as the PWM time base for PWM mode of the CCP module. The TMR2 register is readable and writable, and is cleared on any device Reset. The input clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits T2CKPS<1:0> (T2CON<1:0>). The Timer2 module has an 8-bit period register PR2.
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PIC16F627A/628A/648A REGISTER 8-1: T2CON – TIMER2 CONTROL REGISTER (ADDRESS: 12h) U-0 R/W-0 — R/W-0 R/W-0 R/W-0 TOUTPS3 TOUTPS2 TOUTPS1 R/W-0 TOUTPS0 R/W-0 R/W-0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS<3:0>: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale Value 0001 = 1:2 Postscale Value • • • 1111 = 1:16 Postscale bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00
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PIC16F627A/628A/648A 9.0 CAPTURE/COMPARE/PWM (CCP) MODULE TABLE 9-1: The CCP (Capture/Compare/PWM) module contains a 16-bit register which can operate as a 16-bit Capture register, as a 16-bit Compare register or as a PWM master/slave Duty Cycle register. Table 9-1 shows the timer resources of the CCP module modes.
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PIC16F627A/628A/648A 9.1 9.1.4 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RB3/CCP1. An event is defined as: • • • • Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge An event is selected by control bits CCP1M<3:0> (CCP1CON<3:0>). When a capture is made, the interrupt request flag bit CCP1IF (PIR1<2>) is set. It must be cleared in software.
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PIC16F627A/628A/648A 9.2.1 CCP PIN CONFIGURATION 9.2.4 The user must configure the RB3/CCP1 pin as an output by clearing the TRISB<3> bit. Note: 9.2.2 In this mode (CCP1M<3:0>=1011), an internal hardware trigger is generated, which may be used to initiate an action. See Register 9-1. Clearing the CCP1CON register will force the RB3/CCP1 compare output latch to the default low level. This is not the data latch.
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PIC16F627A/628A/648A 9.3 PWM Mode In Pulse Width Modulation (PWM) mode, the CCP1 pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTB data latch, the TRISB<3> bit must be cleared to make the CCP1 pin an output. A PWM output (Figure 9-4) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (frequency = 1/period).
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PIC16F627A/628A/648A 9.3.2 PWM DUTY CYCLE Maximum PWM resolution (bits) for a given PWM frequency: The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available: the CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>.
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PIC16F627A/628A/648A 10.0 COMPARATOR MODULE The comparator module contains two analog comparators. The inputs to the comparators are multiplexed with the RA0 through RA3 pins. The on-chip Voltage Reference (Section 11.0 “Voltage Reference Module”) can also be an input to the comparators. REGISTER 10-1: The CMCON register, shown in Register 10-1, controls the comparator input and output multiplexers. A block diagram of the comparator is shown in Figure 10-1.
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PIC16F627A/628A/648A 10.1 If the Comparator mode is changed, the comparator output level may not be valid for the specified mode change delay shown in Table 17-2. Comparator Configuration There are eight modes of operation for the comparators. The CMCON register is used to select the mode. Figure 10-1 shows the eight possible modes. The TRISA register controls the data direction of the comparator pins for each mode.
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PIC16F627A/628A/648A The code example in Example 10-1 depicts the steps required to configure the Comparator module. RA3 and RA4 are configured as digital output. RA0 and RA1 are configured as the V- inputs and RA2 as the V+ input to both comparators. EXAMPLE 10-1: BCF BSF BSF BCF BSF BSF 10.
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PIC16F627A/628A/648A 10.5 Comparator Outputs The comparator outputs are read through the CMCON register. These bits are read-only. The comparator outputs may also be directly output to the RA3 and RA4 I/O pins. When the CM<2:0> = 110 or 001, multiplexors in the output path of the RA3 and RA4/T0CK1/CMP2 pins will switch and the output of each pin will be the unsynchronized output of the comparator.
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PIC16F627A/628A/648A 10.6 Comparator Interrupts The comparator interrupt flag is set whenever there is a change in the output value of either comparator. Software will need to maintain information about the status of the output bits, as read from CMCON<7:6>, to determine the actual change that has occurred. The CMIF bit, PIR1<6>, is the comparator interrupt flag. The CMIF bit must be reset by clearing ‘0’. Since it is also possible to write a ‘1’ to this register, a simulated interrupt may be initiated.
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PIC16F627A/628A/648A FIGURE 10-4: ANALOG INPUT MODE VDD VT = 0.6V RS < 10 K AIN CPIN 5 pF VA VT = 0.
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PIC16F627A/628A/648A 11.0 The equations used to calculate the output of the Voltage Reference module are as follows: VOLTAGE REFERENCE MODULE if VRR = 1: The Voltage Reference module consists of a 16-tap resistor ladder network that provides a selectable voltage reference. The resistor ladder is segmented to provide two ranges of VREF values and has a power-down function to conserve power when the reference is not being used.
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PIC16F627A/628A/648A FIGURE 11-1: VOLTAGE REFERENCE BLOCK DIAGRAM VDD VREN 16 Stages 8R R R R R 8R VSS VREF Note: 11.2 0x02 CMCON STATUS,RP0 0x07 TRISA 0xA6 VRCON STATUS,RP0 DELAY10 VOLTAGE REFERENCE CONFIGURATION ;4 Inputs Muxed ;to 2 comps. ;go to Bank 1 ;RA3-RA0 are ;outputs ;enable VREF ;low range set VR<3:0>=6 ;go to Bank 0 ;10μs delay Voltage Reference Accuracy/Error The full range of VSS to VDD cannot be realized due to the construction of the module.
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PIC16F627A/628A/648A FIGURE 11-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE R(1) VREF Op Amp RA2 + Module VREF Output Voltage Reference Output Impedance Note 1: R is dependent upon the voltage reference configuration VRCON<3:0> and VRCON<5>.
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PIC16F627A/628A/648A 12.0 The USART can be configured in the following modes: UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART) MODULE • Asynchronous (full-duplex) • Synchronous – Master (half-duplex) • Synchronous – Slave (half-duplex) The Universal Synchronous Asynchronous Receiver Transmitter (USART) is also known as a Serial Communications Interface (SCI).
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PIC16F627A/628A/648A REGISTER 12-2: RCSTA – RECEIVE STATUS AND CONTROL REGISTER (ADDRESS: 18h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADEN FERR OERR RX9D bit 7 bit 0 bit 7 SPEN: Serial Port Enable bit (Configures RB1/RX/DT and RB2/TX/CK pins as serial port pins when bits TRISB<2:1> are set) 1 = Serial port enabled 0 = Serial port disabled bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable
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PIC16F627A/628A/648A 12.1 EQUATION 12-1: USART Baud Rate Generator (BRG) The BRG supports both the Asynchronous and Synchronous modes of the USART. It is a dedicated 8-bit baud rate generator. The SPBRG register controls the period of a free running 8-bit timer. In Asynchronous mode, bit BRGH (TXSTA<2>) also controls the baud rate. In Synchronous mode, bit BRGH is ignored.
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PIC16F627A/628A/648A TABLE 12-3: BAUD RATES FOR SYNCHRONOUS MODE KBAUD ERROR SPBRG value (decimal) KBAUD ERROR SPBRG value (decimal) KBAUD ERROR SPBRG value (decimal) 0.3 NA — — NA — — NA — — 1.2 NA 2.4 NA — — NA — — NA — — NA — — — — NA — 9.6 NA — — — NA — — 9.766 +1.73% 255 19.2 19.53 +1.73% 255 19.23 +0.16% 207 19.23 +0.16% 129 76.8 76.92 96 96.15 +0.16% 64 76.92 +0.16% 51 75.76 -1.36% 32 +0.16% 51 95.24 -0.79% 41 96.15 +0.
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PIC16F627A/628A/648A TABLE 12-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0) KBAUD ERROR SPBRG value (decimal) 0.3 NA — 1.2 1.221 2.4 2.404 9.6 19.2 BAUD RATE (K) FOSC = 20 MHz 16 MHz KBAUD ERROR SPBRG value (decimal) — NA — +1.73% 255 1.202 +0.16% 129 2.404 9.469 -1.36% 32 19.53 +1.73% 10 MHz KBAUD ERROR SPBRG value (decimal) — NA — — +0.16% 207 1.202 +0.16% 129 +0.16% 103 2.404 +0.16% 64 9.615 +0.16% 25 9.766 +1.73% 15 15 19.23 +0.16% 12 19.
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PIC16F627A/628A/648A TABLE 12-5: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1) KBAUD ERROR SPBRG value (decimal) 9.615 +0.16% 19200 19.230 38400 37.878 BAUD RATE (K) 9600 FOSC = 20 MHz 16 MHz KBAUD ERROR SPBRG value (decimal) 129 9.615 +0.16% 103 +0.16% 64 19.230 +0.16% -1.36% 32 38.461 +0.16% 10 MHz KBAUD ERROR SPBRG value (decimal) 9.615 +0.16% 64 51 18.939 -1.36% 32 25 39.062 +1.7% 15 57600 56.818 -1.36% 21 58.823 +2.12% 16 56.818 -1.36% 10 115200 113.
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PIC16F627A/628A/648A 12.2 USART Asynchronous Mode In this mode, the USART uses standard non-return-tozero (NRZ) format (one Start bit, eight or nine data bits and one Stop bit). The most common data format is 8-bit. A dedicated 8-bit baud rate generator is used to derive baud rate frequencies from the oscillator. The USART transmits and receives the LSb first. The USART’s transmitter and receiver are functionally independent, but use the same data format and baud rate.
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PIC16F627A/628A/648A FIGURE 12-1: USART TRANSMIT BLOCK DIAGRAM Data Bus TXIF TXREG register TXIE 8 MSb (8) LSb 0 ² ² ² Pin Buffer and Control TSR register RB2/TX/CK pin Interrupt TXEN Baud Rate CLK TRMT SPEN SPBRG TX9 Baud Rate Generator TX9D Follow these steps when setting up an Asynchronous Transmission: 1. 2. 3. 4. 5. 6. 7. 8. TRISB<1> and TRISB<2> should both be set to ‘1’ to configure the RB1/RX/DT and RB2/TX/CK pins as inputs.
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PIC16F627A/628A/648A FIGURE 12-3: ASYNCHRONOUS TRANSMISSION (BACK TO BACK) Write to TXREG Word 1 BRG output (shift clock) RB2/TX/CK (pin) Word 2 Start bit TXIF bit (interrupt reg. flag) TRMT bit (Transmit shift reg. empty flag) bit 0 bit 1 Word 1 bit 7/8 Word 1 Transmit Shift Reg. Start bit Word 2 Stop bit bit 0 Word 2 Transmit Shift Reg. . Note: This timing diagram shows two consecutive transmissions.
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PIC16F627A/628A/648A 12.2.2 USART ASYNCHRONOUS RECEIVER double buffered register (i.e., it is a two-deep FIFO). It is possible for two bytes of data to be received and transferred to the RCREG FIFO and a third byte begin shifting to the RSR register. On the detection of the Stop bit of the third byte, if the RCREG register is still full, then overrun error bit OERR (RCSTA<1>) will be set. The word in the RSR will be lost. The RCREG register can be read twice to retrieve the two bytes in the FIFO.
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PIC16F627A/628A/648A FIGURE 12-5: ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT Start bit RB1/RX/DT (Pin) bit 0 bit 1 bit 8 Stop bit Start bit bit 0 bit 8 Stop bit RCV Shift Reg RCV Buffer Reg bit 8 = 0, Data Byte bit 8 = 1, Address Byte Read RCV Buffer Reg RCREG Word 1 RCREG RCIF (interrupt flag) ADEN = 1 (Address Match Enable) Note: ‘1’ ‘1’ This timing diagram shows a data byte followed by an address byte.
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PIC16F627A/628A/648A Follow these steps when setting up an Asynchronous Reception: 1. TRISB<1> and TRISB<2> should both be set to ‘1’ to configure the RB1/RX/DT and RB2/TX/CK pins as inputs. Output drive, when required, is controlled by the peripheral circuitry. 2. Initialize the SPBRG register for the appropriate baud rate. If a high-speed baud rate is desired, set bit BRGH. (Section 12.1 “USART Baud Rate Generator (BRG)”). 3. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN.
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PIC16F627A/628A/648A 12.3 The ADEN bit will only take effect when the receiver is configured in 9-bit mode (RX9 = 1). When ADEN is disabled (= 0), all data bytes are received and the 9th bit can be used as the parity bit. USART Address Detect Function 12.3.1 USART 9-BIT RECEIVER WITH ADDRESS DETECT The receive block diagram is shown in Figure 12-4. When the RX9 bit is set in the RCSTA register, 9 bits are received and the ninth bit is placed in the RX9D bit of the RCSTA register.
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PIC16F627A/628A/648A 12.4 USART Synchronous Master Mode In Synchronous Master mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit SYNC (TXSTA<4>). In addition enable bit SPEN (RCSTA<7>) is set in order to configure the RB2/TX/CK and RB1/RX/DT I/O pins to CK (clock) and DT (data) lines, respectively.
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PIC16F627A/628A/648A TABLE 12-9: Address REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Name Bit 7 Bit 6 Bit 5 Bit 4 TXIF 0Ch PIR1 EEIF CMIF RCIF 18h RCSTA SPEN RX9 SREN CREN 19h TXREG USART Transmit Data Register 8Ch PIE1 EEIE CMIE RCIE 98h TXSTA CSRC TX9 99h SPBRG Baud Rate Generator Register Bit 3 — Bit 2 — TXEN SYNC — Bit 0 Value on POR CCP1IF TMR2IF TMR1IF 0000 -000 ADEN TXIE Bit 1 FERR OERR RX9D TRMT TX9D 0000 -000 0000 000x 0000 000x 0000 00
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PIC16F627A/628A/648A 12.4.2 USART SYNCHRONOUS MASTER RECEPTION Follow these steps when setting up a Synchronous Master Reception: 1. TRISB<1> and TRISB<2> should both be set to ‘1’ to configure the RB1/RX/DT and RB2/TX/CK pins as inputs. Output drive, when required, is controlled by the peripheral circuitry. 2. Initialize the SPBRG register for the appropriate baud rate. (Section 12.1 “USART Baud Rate Generator (BRG)”). 3. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. 4.
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PIC16F627A/628A/648A FIGURE 12-10: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2 Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3 Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4 RB1/RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 RB2/TX/CK pin WRITE to Bit SREN SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RXREG Note: 12.5 Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRG = 0.
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PIC16F627A/628A/648A 12.5.2 USART SYNCHRONOUS SLAVE RECEPTION Follow these steps when setting up a Synchronous Slave Reception: 1. The operation of the Synchronous Master and Slave modes is identical except in the case of the Sleep mode. Also, bit SREN is a “don’t care” in Slave mode. If receive is enabled by setting bit CREN prior to the SLEEP instruction, then a word may be received during Sleep.
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PIC16F627A/628A/648A 13.0 DATA EEPROM MEMORY The EEPROM data memory is readable and writable during normal operation (full VDD range). This memory is not directly mapped in the register file space. Instead it is indirectly addressed through the Special Function Registers (SFRs). There are four SFRs used to read and write this memory.
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PIC16F627A/628A/648A 13.1 EEADR 13.2 EECON1 and EECON2 Registers The PIC16F648A EEADR register addresses 256 bytes of data EEPROM. All eight bits in the register (EEADR<7:0>) are required. EECON1 is the control register with four low order bits physically implemented. The upper-four bits are nonexistent and read as ‘0’s. The PIC16F627A/628A EEADR register addresses only the first 128 bytes of data EEPROM so only seven of the eight bits in the register (EEADR<6:0>) are required.
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PIC16F627A/628A/648A 13.3 Reading the EEPROM Data Memory To read a data memory location, the user must write the address to the EEADR register and then set control bit RD (EECON1<0>). The data is available, in the very next cycle, in the EEDATA register; therefore it can be read in the next instruction. EEDATA will hold this value until another read or until it is written to by the user (during a write operation).
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PIC16F627A/628A/648A 13.7 Using the Data EEPROM The data EEPROM is a high endurance, byte addressable array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often).
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PIC16F627A/628A/648A 13.8 Data EEPROM Operation During Code-Protect When the device is code-protected, the CPU is able to read and write data to the data EEPROM. TABLE 13-1: REGISTERS/BITS ASSOCIATED WITH DATA EEPROM Value on Power-on Reset Value on all other Resets xxxx xxxx xxxx xxxx ---- x000 uuuu uuuu uuuu uuuu ---- q000 ---- ---9Dh EECON2(1) EEPROM Control Register 2 Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’, q = value depends upon condition.
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PIC16F627A/628A/648A 14.0 SPECIAL FEATURES OF THE CPU Special circuits to deal with the needs of real-time applications are what sets a microcontroller apart from other processors. The PIC16F627A/628A/648A family has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power-saving operating modes and offer code protection. These are: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12.
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PIC16F627A/628A/648A REGISTER 14-1: CP — CONFIG – CONFIGURATION WORD REGISTER — — — CPD LVP BOREN MCLRE FOSC2 PWRTE WDTE F0SC1 bit 13 F0SC0 bit 0 bit 13: CP: Flash Program Memory Code Protection bit(2) (PIC16F648A) 1 = Code protection off 0 = 0000h to 0FFFh code-protected (PIC16F628A) 1 = Code protection off 0 = 0000h to 07FFh code-protected (PIC16F627A) 1 = Code protection off 0 = 0000h to 03FFh code-protected bit 12-9: Unimplemented: Read as ‘0’ bit 8: CPD: Data Code Protection bit(3)
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PIC16F627A/628A/648A 14.2 TABLE 14-1: Oscillator Configurations 14.2.1 OSCILLATOR TYPES The PIC16F627A/628A/648A can be operated in eight different oscillator options. The user can program three configuration bits (FOSC2 through FOSC0) to select one of these eight modes: • • • • • • LP Low Power Crystal XT Crystal/Resonator HS High Speed Crystal/Resonator RC External Resistor/Capacitor (2 modes) INTOSC Internal Precision Oscillator (2 modes) EC External Clock In 14.2.
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PIC16F627A/628A/648A 14.2.3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT Either a prepackaged oscillator can be used or a simple oscillator circuit with TTL gates can be built. Prepackaged oscillators provide a wide operating range and better stability. A well-designed crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator circuits can be used; one with series resonance, or one with parallel resonance.
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PIC16F627A/628A/648A 14.2.6 RC OSCILLATOR 14.2.8 For applications where precise timing is not a requirement, the RC oscillator option is available. The operation and functionality of the RC oscillator is dependent upon a number of variables. The RC oscillator frequency is a function of: • Supply voltage • Resistor (REXT) and capacitor (CEXT) values • Operating temperature The oscillator frequency will vary from unit-to-unit due to normal process parameter variation.
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PIC16F627A/628A/648A FIGURE 14-6: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT External Reset Schmitt Trigger Input MCLR/ VPP Pin Sleep WDT Module VDD Rise Detect WDT Time-out Reset Power-on Reset VDD Brown-out Reset S Q R Q BOREN OST/PWRT OST Chip_Reset 10-bit Ripple-counter OSC1/ CLKIN Pin PWRT On-chip(1) OSC 10-bit Ripple-counter Enable PWRT See Table 14-3 for time out situations. Enable OST Note 1: This is a separate oscillator from the INTOSC/RC oscillator.
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PIC16F627A/628A/648A 14.4 14.4.1 14.4.3 Power-on Reset (POR), Power-up Timer (PWRT), Oscillator Start-up Timer (OST) and Brown-out Reset (BOR) The OST provides a 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over. Program execution will not start until the OST time out is complete. This ensures that the crystal oscillator or resonator has started and stabilized. POWER-ON RESET (POR) The on-chip POR holds the part in Reset until a VDD rise is detected (in the range of 1.2-1.7V).
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PIC16F627A/628A/648A 14.4.5 TIME OUT SEQUENCE 14.4.6 On power-up, the time out sequence is as follows: First PWRT time-out is invoked after POR has expired. Then OST is activated. The total time out will vary based on oscillator configuration and PWRTE bit Status. For example, in RC mode with PWRTE bit set (PWRT disabled), there will be no time out at all. Figure 14-8, Figure 14-11 and Figure 14-12 depict time out sequences. The PCON/Status register, PCON (address 8Eh), has two bits.
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PIC16F627A/628A/648A TABLE 14-5: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT RESET Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset Value on all other Resets(1) 03h, 83h, 103h, 183h STATUS IRP RP1 RPO TO PD Z DC C 0001 1xxx 000q quuu PCON — — — — OSCF — POR BOR ---- 1-0x ---- u-uq 8Eh Legend: Note 1: x = unknown, u = unchanged, - = unimplemented read as ‘0’, q = value depends upon condition.
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PIC16F627A/628A/648A TABLE 14-7: Register INITIALIZATION CONDITION FOR REGISTERS Address Power-on Reset W • MCLR Reset during normal operation • MCLR Reset during Sleep • WDT Reset • Brown-out Reset (1) • Wake-up from Sleep(7) through interrupt • Wake-up from Sleep(7) through WDT time out — xxxx xxxx uuuu uuuu uuuu uuuu INDF 00h, 80h, 100h, 180h — — — TMR0 01h, 101h xxxx xxxx uuuu uuuu uuuu uuuu PCL 02h, 82h, 102h, 182h 0000 0000 0000 0000 PC + 1(3) STATUS 03h, 83h, 103h, 183h 0
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PIC16F627A/628A/648A FIGURE 14-8: TIME OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE VDD MCLR Internal POR TPWRT PWRT Time Out TOST OST Time Out Internal Reset TIME OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 FIGURE 14-9: VDD MCLR Internal POR TPWRT PWRT Time Out TOST OST Time Out Internal Reset FIGURE 14-10: TIME OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) VDD MCLR Internal POR TPWRT PWRT Time Out TOST OST Time Out Internal Reset © 2009 Microchip Technology Inc.
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PIC16F627A/628A/648A FIGURE 14-11: EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP) VDD VDD FIGURE 14-13: EXTERNAL BROWN-OUT PROTECTION CIRCUIT 2 VDD VDD R1 Q1 D R MCLR PIC16F627A/628A/648A R2 R1 40k MCLR PIC16F627A/628A/648A C Note 1: 2: 3: External Power-on Reset circuit is required only if VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down.
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PIC16F627A/628A/648A 14.5 When an interrupt is responded to, the GIE is cleared to disable any further interrupt, the return address is pushed into the stack and the PC is loaded with 0004h. Once in the interrupt service routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid RB0/ INT recursive interrupts.
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PIC16F627A/628A/648A 14.5.1 RB0/INT INTERRUPT 14.5.3 External interrupt on the RB0/INT pin is edge triggered; either rising if INTEDG bit (OPTION<6>) is set, or falling, if INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, the INTF bit (INTCON<1>) is set. This interrupt can be disabled by clearing the INTE control bit (INTCON<4>). The INTF bit must be cleared in software in the interrupt service routine before re-enabling this interrupt.
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PIC16F627A/628A/648A TABLE 14-8: Address SUMMARY OF INTERRUPT REGISTERS Name 0Bh, 8Bh, INTCON 10Bh, 18Bh Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset Value on all other Resets(1) GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 EEIF CMIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000 8Ch PIE1 EEIE CMIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000 Note 1: Other (non Power-up) Resets include MCLR Reset, Brown-ou
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PIC16F627A/628A/648A FIGURE 14-16: WATCHDOG TIMER BLOCK DIAGRAM From TMR0 Clock Source (Figure 6-1) 0 M U 1X Watchdog Timer WDT Postscaler/ TMR0 Prescaler 8 8 to 1 MUX PSA 3 PS<2:0> WDT Enable Bit To TMR0 (Figure 6-1) 0 MUX 1 PSA WDT Time-out T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.
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PIC16F627A/628A/648A 14.8.1 WAKE-UP FROM SLEEP The device can wake-up from Sleep through one of the following events: 1. 2. 3. External Reset input on MCLR pin Watchdog Timer wake-up (if WDT was enabled) Interrupt from RB0/INT pin, RB port change, or any peripheral interrupt, which is active in Sleep. The first event will cause a device Reset. The two latter events are considered a continuation of program execution.
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PIC16F627A/628A/648A 14.11 In-Circuit Serial Programming™ (ICSP™) The PIC16F627A/628A/648A microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product.
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PIC16F627A/628A/648A 14.13 In-Circuit Debugger Since in-circuit debugging requires the loss of clock, data and MCLR pins, MPLAB® ICD 2 development with an 18-pin device is not practical. A special 28-pin PIC16F648A-ICD device is used with MPLAB ICD 2 to provide separate clock, data and MCLR pins and frees all normally available pins to the user. Debugging of all three versions of the PIC16F627A/628A/648A is supported by the PIC16F648A-ICD.
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PIC16F627A/628A/648A 15.0 INSTRUCTION SET SUMMARY Each PIC16F627A/628A/648A instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC16F627A/628A/648A instruction set summary in Table 15-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 15-1 shows the opcode field descriptions.
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PIC16F627A/628A/648A TABLE 15-2: PIC16F627A/628A/648A INSTRUCTION SET Mnemonic, Operands 14-Bit Opcode Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f — f, d f, d f, d f, d f, d f, d f, d f — f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive O
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PIC16F627A/628A/648A 15.2 Instruction Descriptions ADDLW Add Literal and W AND Literal with W Syntax: [ label ] ADDLW Syntax: [ label ] ANDLW Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ k ≤ 255 Operation: (W) + k → (W) Operation: (W) .AND. (k) → (W) Status Affected: C, DC, Z Encoding: Status Affected: Z 11 Description: The contents of the W register are added to the eight bit literal ‘k’ and the result is placed in the W register.
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PIC16F627A/628A/648A BCF Bit Clear f BTFSC Bit Test f, Skip if Clear Syntax: [ label ] BCF Syntax: [ label ] BTFSC f,b Operands: 0 ≤ f ≤ 127 0≤b≤7 Operands: 0 ≤ f ≤ 127 0≤b≤7 Operation: 0 → (f) Operation: skip if (f) = 0 Status Affected: None Status Affected: None Encoding: 01 Description: Bit ‘b’ in register ‘f’ is cleared.
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PIC16F627A/628A/648A BTFSS Bit Test f, Skip if Set CALL Call Subroutine Syntax: [ label ] BTFSS f,b Syntax: [ label ] CALL k Operands: 0 ≤ f ≤ 127 0≤b<7 Operands: 0 ≤ k ≤ 2047 Operation: Operation: skip if (f) = 1 Status Affected: None (PC)+ 1→ TOS, k → PC<10:0>, (PCLATH<4:3>) → PC<12:11> Encoding: 01 Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘1’, then the next instruction is skipped.
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PIC16F627A/628A/648A CLRW Clear W COMF Complement f Syntax: [ label ] CLRW Syntax: [ label ] COMF Operands: None Operands: Operation: 00h → (W) 1→Z 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) → (dest) Status Affected: Z Status Affected: Z Encoding: 00 Encoding: 00 Description: W register is cleared. Zero bit (Z) is set. Description: Words: 1 Cycles: 1 The contents of register ‘f’ are complemented. If ‘d’ is ‘0’, the result is stored in W.
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PIC16F627A/628A/648A DECFSZ Decrement f, Skip if 0 GOTO Unconditional Branch Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ k ≤ 2047 Operation: (f) - 1 → (dest); 0 Operation: k → PC<10:0> PCLATH<4:3> → PC<12:11> Status Affected: None Status Affected: None Encoding: Encoding: 10 00 Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in the W register.
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PIC16F627A/628A/648A INCF Increment f INCFSZ Increment f, Skip if 0 Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) + 1 → (dest) Operation: (f) + 1 → (dest), skip if result = 0 Status Affected: Z Status Affected: None Encoding: 00 Encoding: 00 Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’.
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PIC16F627A/628A/648A IORLW Inclusive OR Literal with W MOVLW Move Literal to W Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ k ≤ 255 Operation: (W) .OR. k → (W) Operation: k → (W) Status Affected: Z Status Affected: None Encoding: 11 Encoding: 11 Description: The contents of the W register is OR’ed with the eight-bit literal ‘k’. The result is placed in the W register. Description: The eight bit literal ‘k’ is loaded into W register.
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PIC16F627A/628A/648A MOVWF Move W to f Syntax: [ label ] MOVWF f OPTION Load Option Register Syntax: [ label ] None OPTION Operands: 0 ≤ f ≤ 127 Operands: Operation: (W) → (f) Operation: (W) → OPTION Status Affected: None Status Affected: None Encoding: 00 Encoding: 00 Description: Move data from W register to register ‘f’. Description: Words: 1 Cycles: 1 Example MOVWF The contents of the W register are loaded in the OPTION register.
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PIC16F627A/628A/648A RETLW Return with Literal in W RLF Rotate Left f through Carry Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ k ≤ 255 Operands: Operation: k → (W); TOS → PC 0 ≤ f ≤ 127 d ∈ [0,1] Operation: See description below Status Affected: None Status Affected: C Encoding: 11 Encoding: 00 Description: The W register is loaded with the eight-bit literal ‘k’. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction.
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PIC16F627A/628A/648A RRF Rotate Right f through Carry SUBLW Subtract W from Literal Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ k ≤ 255 Operation: k - (W) → (W) Operation: See description below C, DC, Z Status Affected: C Status Affected: Encoding: 00 Encoding: 11 Description: The contents of register ‘f’ are rotated one bit to the right through the Carry Flag. If ‘d’ is ‘0’, the result is placed in the W register.
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PIC16F627A/628A/648A SUBWF Subtract W from f SWAPF Swap Nibbles in f Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) - (W) → (dest) Operation: Status Affected: C, DC, Z (f<3:0>) → (dest<7:4>), (f<7:4>) → (dest<3:0>) Status Affected: None Encoding: 00 Encoding: 00 Description: Subtract (2’s complement method) W register from register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register.
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PIC16F627A/628A/648A XORLW Exclusive OR Literal with W XORWF Exclusive OR W with f Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (W) .XOR. (f) → (dest) Status Affected: Z Encoding: 00 Description: Exclusive OR the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’.
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PIC16F627A/628A/648A 16.
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PIC16F627A/628A/648A 16.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 16.
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PIC16F627A/628A/648A 16.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
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PIC16F627A/628A/648A 16.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 16.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
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PIC16F627A/628A/648A 17.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings(†) Ambient temperature under bias................................................................................................................. -40 to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on VDD with respect to VSS ..........................................................................
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PIC16F627A/628A/648A PIC16F627A/628A/648A VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C FIGURE 17-1: 6.0 5.5 5.0 VDD (VOLTS) 4.5 4.0 3.5 3.0 2.5 4 0 10 20 25 FREQUENCY (MHz) The shaded region indicates the permissible combinations of voltage and frequency. Note: PIC16LF627A/628A/648A VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +85°C FIGURE 17-2: 6.0 5.5 5.0 4.5 VDD (VOLTS) 4.0 3.5 3.0 2.5 2.
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PIC16F627A/628A/648A 17.1 DC Characteristics: PIC16F627A/628A/648A (Industrial, Extended) PIC16LF627A/628A/648A (Industrial) PIC16LF627A/628A/648A (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ Ta ≤ +85°C for industrial PIC16F627A/628A/648A (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ Ta ≤ +85°C for industrial and -40°C ≤ Ta ≤ +125°C for extended Param No.
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PIC16F627A/628A/648A 17.2 DC Characteristics: PIC16F627A/628A/648A (Industrial) PIC16LF627A/628A/648A (Industrial) DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ Ta ≤ +85°C for industrial Param No. Min† LF and F Device Characteristics Conditions Typ Max Units Note VDD Supply Voltage (VDD) D001 LF 2.0 — 5.5 V — LF/F 3.0 — 5.5 V — LF — 0.01 0.80 μA 2.0 LF/F — 0.01 0.85 μA 3.0 — 0.02 2.7 μA 5.0 LF — 1 2.
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PIC16F627A/628A/648A 17.3 DC Characteristics: PIC16F627A/628A/648A (Extended) DC CHARACTERISTICS Param No. Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ Ta ≤ +125°C for extended Conditions Device Characteristics Min† Typ Max Units Note VDD Supply Voltage (VDD) D001 — 3.0 — 5.5 V — — 0.01 4 μA 3.0 — 0.02 8 μA 5.0 WDT, BOR, Comparators, VREF and T1OSC: disabled — — 2 9 μA 3.0 WDT Current — 9 20 μA 5.0 — — 29 52 μA 4.
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PIC16F627A/628A/648A 17.4 DC Characteristics: PIC16F627A/628A/648A (Industrial, Extended) PIC16LF627A/628A/648A (Industrial) DC CHARACTERISTICS Param. No. Sym VIL Characteristic/Device Min Typ† Max Unit VSS VSS VSS VSS — — — — 0.8 0.15 VDD 0.2 VDD 0.2 VDD V V V V VSS VSS — — 0.3 VDD 0.6 V V 2.0V .25 VDD + 0.8V 0.8 VDD 0.8 VDD 1.3 0.9 VDD 0.7 VDD — — — — — — VDD VDD VDD VDD VDD VDD VDD V V V V V V V VDD = 4.5V to 5.5V otherwise 50 200 400 μA VDD = 5.
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PIC16F627A/628A/648A TABLE 17-1: DC Characteristics: PIC16F627A/628A/648A (Industrial, Extended) PIC16LF627A/628A/648A (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial and -40°C ≤ TA ≤ +125°C for extended Operating voltage VDD range as described in DC specification Table 17-2 and Table 17-3 DC CHARACTERISTICS Parameter No. Sym Characteristic Min Typ† Max Units 100K 10K VMIN 1M 100K — — 5.
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PIC16F627A/628A/648A TABLE 17-2: COMPARATOR SPECIFICATIONS Operating Conditions: 2.0V < VDD <5.5V, -40°C < TA < +125°C, unless otherwise stated. Param No. Characteristics Sym Min Typ Max Units D300 Input Offset Voltage VIOFF — ±5.0 ±10 mV D301 Input Common Mode Voltage VICM 0 — VDD – 1.
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PIC16F627A/628A/648A 17.5 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2.
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PIC16F627A/628A/648A 17.6 Timing Diagrams and Specifications FIGURE 17-4: EXTERNAL CLOCK TIMING Q4 Q1 Q3 Q2 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 17-4: Parameter No. EXTERNAL CLOCK TIMING REQUIREMENTS Sym FOSC Characteristic External CLKIN Frequency(1) Oscillator Frequency(1) 1 TOSC External CLKIN Period(1) Oscillator Period(1) 2 TCY 3 TosL, TosH 4 RC Min Typ† Max Units Conditions DC — 4 MHz XT and RC Osc mode, VDD = 5.
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PIC16F627A/628A/648A TABLE 17-5: PRECISION INTERNAL OSCILLATOR PARAMETERS Parameter No. Sym F10 FIOSC Oscillator Center frequency F13 ΔIOSC Oscillator Accuracy F14* Characteristic TIOSCST Oscillator Wake-up from Sleep start-up time Min Typ Max Units Conditions — 4 — MHz 3.96 4 4.04 MHz VDD = 3.5 V, 25°C 3.92 4 4.08 MHz 2.0V ≤ VDD ≤ 5.5V 0°C ≤ TA ≤ +85°C 3.80 4 4.20 MHz 2.0V ≤ VDD ≤ 5.5V -40°C ≤ TA ≤ +85°C (IND) -40°C ≤ TA ≤ +125°C (EXT) — 6 8 μs VDD = 2.
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PIC16F627A/628A/648A TABLE 17-6: Parameter No.
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PIC16F627A/628A/648A FIGURE 17-7: BROWN-OUT RESET TIMING VBOR VDD 35 TABLE 17-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER REQUIREMENTS Parameter No.
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PIC16F627A/628A/648A TABLE 17-8: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param No. Sym 40 TT0H T0CKI High Pulse Width No Prescaler 41 TT0L T0CKI Low Pulse Width No Prescaler 42 TT0P T0CKI Period 45 TT1H T1CKI High Synchronous, No Prescaler Time Synchronous, PIC16F62XA with Prescaler PIC16LF62XA Characteristic Min Typ† 0.5TCY + 20* — With Prescaler — — ns — — ns 10* — — ns Greater of: 20 or TCY + 40* N — — ns N = prescale value (2, 4, ..., 256) 0.
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PIC16F627A/628A/648A FIGURE 17-9: CAPTURE/COMPARE/PWM TIMINGS RB3/CCP1 (CAPTURE MODE) 50 51 52 RB3/CCP1 (COMPARE OR PWM MODE) 53 TABLE 17-9: CAPTURE/COMPARE/PWM REQUIREMENTS Param Sym No. TCCL CCP input low time 50 54 Characteristic Min No Prescaler PIC16F62XA With Prescaler PIC16LF62XA 51 TCCH CCP input high time No Prescaler PIC16F62XA With Prescaler PIC16LF62XA 52 TCCP CCP input period 53 TCCR CCP output rise time TCCF CCP output fall time 54 Typ† Max Units 0.
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PIC16F627A/628A/648A 18.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range.
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PIC16F627A/628A/648A FIGURE 18-2: TYPICAL BASELINE IPD vs. VDD (85°C) 300 280 260 240 IPD (nA) 220 200 +85°C 180 160 140 120 100 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (Volts) FIGURE 18-3: TYPICAL BASELINE CURRENT IPD vs. VDD (125°C) 2.4 2.2 IPD (μA) 2.0 1.8 +125°C 1.6 1.4 1.2 1.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (Volts) DS40044G-page 152 © 2009 Microchip Technology Inc.
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PIC16F627A/628A/648A FIGURE 18-4: TYPICAL BOR IPD vs. VDD 40 38 36 IPD (μA) 34 125°C 85°C 25°C 0°C -40°C 32 30 28 26 24 22 20 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 VDD (Volts) FIGURE 18-5: TYPICAL SINGLE COMPARATOR IPD vs. VDD 30 25 IPD (μA) 20 125°C 85°C 25°C 0°C -40°C 15 10 5 0 2 2.5 3 3.5 4 4.5 5 5.5 VDD (Volts) © 2009 Microchip Technology Inc.
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PIC16F627A/628A/648A FIGURE 18-6: TYPICAL VREF IPD vs. VDD 100 90 80 IPD (μA) 70 125°C 85°C 25°C 0°C -40°C 60 50 40 30 20 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (Volts) FIGURE 18-7: TYPICAL WDT IPD vs. VDD 16 14 12 IPD (μA) 10 125°C 85°C 25°C 0°C -40°C 8 6 4 2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (Volts) DS40044G-page 154 © 2009 Microchip Technology Inc.
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PIC16F627A/628A/648A FIGURE 18-8: AVERAGE IPD_TIMER1 5 4 3 -40C IPD (uA) 0C 25C 85C 125 2 1 0 2 2.5 3 3.5 4 4.5 5 5.5 VDD (V) FIGURE 18-9: TYPICAL INTERNAL OSCILLATOR FREQUENCY vs. TEMPERATURE VDD = 5 VOLTS 5.0% 4.0% Change from Calibration Target (%) 3.0% 2.0% 1.0% 0.0% -1.0% -2.0% -3.0% -4.0% -5.0% -40 25 85 125 Temperature (ºC) © 2009 Microchip Technology Inc.
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PIC16F627A/628A/648A FIGURE 18-10: TYPICAL INTERNAL OSCILLATOR FREQUENCY vs. TEMPERATURE VDD = 3 VOLTS 5.0% 4.0% Change from Calibration Target (%) 3.0% 2.0% 1.0% 0.0% -1.0% -2.0% -3.0% -4.0% -5.0% -40 25 85 125 Temperature (ºC) FIGURE 18-11: TYPICAL INTERNAL OSCILLATOR FREQUENCY vs. TEMPERATURE VDD = 2 VOLTS 5.0% 4.0% Change from Calibration Target (%) 3.0% 2.0% 1.0% 0.0% -1.0% -2.0% -3.0% -4.0% -5.0% -40 25 85 125 Temperature (ºC) DS40044G-page 156 © 2009 Microchip Technology Inc.
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PIC16F627A/628A/648A FIGURE 18-12: TYPICAL INTERNAL OSCILLATOR DEVIATION vs. VDD AT 25°C – 4 MHz MODE 5.0% 4.0% Change from Calibration Target (%) 3.0% 2.0% 1.0% 0.0% -1.0% -2.0% -3.0% -4.0% -5.0% 2 2.5 3 3.5 4 4.5 5 5.5 VDD (V) FIGURE 18-13: TYPICAL INTERNAL OSCILLATOR FREQUENCY vs. VDD TEMPERATURE = -40°C TO 85°C 5.0% 4.0% Change from Calibration Target (%) 3.0% 2.0% 1.0% 0.0% -1.0% -2.0% -3.0% -4.0% -5.0% 2 2.5 3 3.5 4 4.5 5 5.5 VDD (V) © 2009 Microchip Technology Inc.
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PIC16F627A/628A/648A FIGURE 18-14: INTERNAL OSCILLATOR IDD vs. VDD – 4 MHz MODE 85 C 25 C Avg -40 C 1.40 1.20 IDD (mA) 1.00 0.80 0.60 0.40 0.20 0.00 2 2.5 3 3.5 4 4.5 5 5.5 VDD (V) FIGURE 18-15: TYPICAL INTERNAL OSCILLATOR FREQUENCY vs. VDD AT 25°C – SLOW MODE 60 Oscillator Frequency (kHz) 55 50 45 40 35 30 2 2.5 3 3.5 4 4.5 5 5.5 VDD (V) DS40044G-page 158 © 2009 Microchip Technology Inc.
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PIC16F627A/628A/648A FIGURE 18-16: INTERNAL OSCILLATOR IDD vs. VDD – SLOW MODE 85 C 25 C Avg -40 C 180 160 140 IPD (μA) 120 100 80 60 40 20 0 2 2.5 3 3.5 4 4.5 5 5.5 VDD (V) FIGURE 18-17: SUPPLY CURRENT (IDD vs. VDD, FOSC = 1 MHz (XT OSCILLATOR MODE) 500 450 400 IPD (μA) 350 125°C 85°C 25°C 0°C -40°C 300 250 200 150 100 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (Volts) © 2009 Microchip Technology Inc.
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PIC16F627A/628A/648A FIGURE 18-18: SUPPLY CURRENT (IDD vs. VDD, FOSC = 4 MHz (XT OSCILLATOR MODE) 1000 900 800 IPD (μA) 700 125°C 85°C 25°C 0°C -40°C 600 500 400 300 200 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (Volts) FIGURE 18-19: SUPPLY CURRENT (IDD) vs. VDD, FOSC = 20 MHz (HS OSCILLATOR MODE) 4.0 IDD (mA) 3.5 125°C 85°C 25°C 0°C -40°C 3.0 2.5 2.0 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 VDD (Volts) DS40044G-page 160 © 2009 Microchip Technology Inc.
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PIC16F627A/628A/648A FIGURE 18-20: TYPICAL WDT PERIOD vs. VDD (-40°C TO +125°C) WDT Time-out 50 Time (mS) 45 40 35 -40 30 25 0 20 15 10 5 85 25 125 0 2 2.5 3 3.5 4 4.5 5 5.5 V DD (V) © 2009 Microchip Technology Inc.
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PIC16F627A/628A/648A 19.0 PACKAGING INFORMATION 19.1 Package Marking Information 18-Lead PDIP Example XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 18-Lead SOIC (.300”) XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN 20-Lead SSOP XXXXXXXXXXX XXXXXXXXXXX YYWWNNN 28-Lead QFN XXXXXXXX XXXXXXXX YYWWNNN Legend: XX...
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PIC16F627A/628A/648A 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 N NOTE 1 E1 1 2 3 D E A2 A L c A1 b1 e b eB 6 &! ' ! 9 ' &! 7"') % ! 7,8. 7 7 & ; < & & 7: 1 , = = - 1 ! & & = = .
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PIC16F627A/628A/648A ! " !" # $ %&' !" ( 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 D N E E1 NOTE 1 1 2 3 e b α h h c φ A2 A A1 β L L1 6 &! ' ! 9 ' &! 7"') % ! 99 . . 7 7: 7 ; < & : 8 & = = = = = - # # 4 4 !! & # %% + 1 , : > #& . # # 4 > #& .
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PIC16F627A/628A/648A ) !*+ , ! " !! '& !!" 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 D N E E1 NOTE 1 1 2 e b c A2 A φ A1 L1 6 &! ' ! 9 ' &! 7"') % ! L 99 . . 7 7 7: ; & : 8 & = = ? < & # %% = = : > #& . < < # # 4 > #& .
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PIC16F627A/628A/648A ) - . $ , / 0 121 -. 3 * &'' ( / * 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 D D2 EXPOSED PAD e E b E2 2 2 1 1 N K N NOTE 1 L BOTTOM VIEW TOP VIEW A A3 A1 6 &! ' ! 9 ' &! 7"') % ! 99 . .
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PIC16F627A/628A/648A ) - . $ , / 0 121 -. 3 * &'' ( / * 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 © 2009 Microchip Technology Inc.
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PIC16F627A/628A/648A APPENDIX A: DATA SHEET REVISION HISTORY APPENDIX B: DEVICE DIFFERENCES The differences between the PIC16F627A/628A/648A devices listed in this data sheet are shown in Table B-1. Revision A This is a new data sheet.
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PIC16F627A/628A/648A APPENDIX C: DEVICE MIGRATIONS This section describes the functional and electrical specification differences when migrating between functionally similar devices. (such as from a PIC16F627 to a PIC16F627A). C.1 1. 2. 3. 4. 5. 6. 7. PIC16F627/628 to a PIC16F627A/ 628A ER mode is now RC mode. Code protection for the program memory has changed from code-protect sections of memory to code-protect of the whole memory.
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PIC16F627A/628A/648A THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
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PIC16F627A/628A/648A READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
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PIC16F627A/628A/648A INDEX A A/D Special Event Trigger (CCP)....................................... 59 Absolute Maximum Ratings .............................................. 135 ADDLW Instruction ........................................................... 119 ADDWF Instruction ........................................................... 119 ANDLW Instruction ........................................................... 119 ANDWF Instruction ...........................................................
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PIC16F627A/628A/648A I I/O Ports .............................................................................. 33 Bidirectional ................................................................ 46 Block Diagrams RB0/INT Pin ........................................................ 38 RB1/RX/DT Pin ................................................... 39 RB2/TX/CK Pin ................................................... 39 RB3/CCP1 Pin .................................................... 40 RB4/PGM Pin..........
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PIC16F627A/628A/648A Q Q-Clock ............................................................................... 61 Quick-Turnaround-Production (QTP) Devices ...................... 9 R RC Oscillator ..................................................................... 101 RC Oscillator Mode Block Diagram........................................................... 101 Reader Response ............................................................. 174 Registers CCP1CON (CCP Operation).............................
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PIC16F627A/628A/648A Synchronous Slave Transmit ...................................... 89 V Voltage Reference Configuration............................................................... 69 Voltage Reference Module ......................................... 69 W Watchdog Timer (WDT) .................................................... 111 WWW Address.................................................................. 173 WWW, On-Line Support........................................................
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PIC16F627A/628A/648A PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Device Temperature Range Package Pattern Device: PIC16F627A/628A/648A:Standard VDD range 3.0V to 5.5V PIC16F627A/628A/648AT:VDD range 3.0V to 5.5V (Tape and Reel) PIC16LF627A/628A/648A:VDD range 2.0V to 5.5V PIC16LF627A/628A/648AT:VDD range 2.0V to 5.
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WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.