Datasheet

 2002 Microchip Technology Inc. Preliminary DS40044A-page 75
PIC16F627A/628A/648A
The data on the RB1/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
low level is present at the RX pin. If bit BRGH
(TXSTA<2>) is clear (i.e., at the low baud rates), the
sampling is done on the seventh, eighth and ninth fall-
ing edges of a x16 clock (Figure 12-3). If bit BRGH is
set (i.e., at the high baud rates), the sampling is done
on the 3 clock edges preceding the second rising edge
after the first falling edge of a x4 clock (Figure 12-4 and
Figure 12-5).
FIGURE 12-1: RX PIN SAMPLING SCHEME. BRGH = 0
FIGURE 12-2: RX PIN SAMPLING SCHEME, BRGH = 1
FIGURE 12-3: RX PIN SAMPLING SCHEME, BRGH = 1
RX
Baud CLK
x16 CLK
START bit
bit0
Samples
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3
Baud CLK for all but START bit
(RB1/RX/DT pin)
RX pin
Baud CLK
x4 CLK
Q2, Q4 CLK
START Bit
bit0 bit1
First falling edge after RX pin goes low
Second rising edge
Samples Samples Samples
1234123412
RX pin
Baud CLK
x4 CLK
Q2, Q4 CLK
START Bit
bit0
First falling edge after RX pin goes low
Second rising edge
Samples
12 3 4
Baud CLK for all but START bit