Datasheet
Table Of Contents
- High Performance RISC CPU:
- Special Microcontroller Features:
- Low Power Features:
- Peripheral Features:
- Pin Diagrams
- Most Current Data Sheet
- Errata
- Customer Notification System
- 1.0 General Description
- 2.0 PIC16F627A/628A/648A Device Varieties
- 3.0 Architectural Overview
- 4.0 Memory Organization
- FIGURE 4-1: Program Memory Map and Stack
- TABLE 4-1: general purpose STATIC ram Registers
- TABLE 4-2: Access to Banks of Registers
- FIGURE 4-2: Data Memory Map of the PIC16F627A and PIC16F628A
- FIGURE 4-3: Data Memory Map of the PIC16F648A
- TABLE 4-3: Special Registers Summary Bank0
- TABLE 4-4: Special Function Registers Summary Bank1
- TABLE 4-5: Special Function Registers Summary Bank2
- TABLE 4-6: Special Function Registers Summary Bank3
- FIGURE 4-4: Loading Of PC In Different Situations
- FIGURE 4-5: Direct/Indirect Addressing PIC16F627A/628A/648A
- 5.0 I/O Ports
- FIGURE 5-1: Block Diagram of RA0/AN0:RA1/AN1 Pins
- FIGURE 5-2: Block Diagram of RA2/Vref Pin
- FIGURE 5-3: Block Diagram of the RA3/AN3 Pin
- FIGURE 5-4: Block Diagram of RA4/T0CKI Pin
- FIGURE 5-5: Block Diagram of the RA5/MCLR/Vpp Pin
- FIGURE 5-6: Block Diagram of RA6/OSC2/CLKOUT Pin
- FIGURE 5-7: Block Diagram of RA7/OSC1/CLKIN Pin
- TABLE 5-1: PORTA Functions
- TABLE 5-2: Summary of Registers Associated with PORTA(1)
- FIGURE 5-8: Block Diagram of RB0/INT Pin
- FIGURE 5-9: Block Diagram of RB1/RX/DT Pin
- FIGURE 5-10: Block Diagram of RB2/TX/CK Pin
- FIGURE 5-11: Block Diagram of RB3/CCP1 Pin
- FIGURE 5-12: Block Diagram of RB4/PGM Pin
- FIGURE 5-13: Block Diagram of RB5 Pin
- FIGURE 5-14: Block Diagram of RB6/T1OSO/T1CKI Pin
- FIGURE 5-15: Block Diagram of the RB7/T1OSI Pin
- TABLE 5-3: PORTB Functions
- TABLE 5-4: Summary of Registers Associated With PORTB(1)
- FIGURE 5-16: Successive I/O Operation
- 6.0 Timer0 Module
- 7.0 Timer1 Module
- 8.0 Timer2 Module
- 9.0 Capture/Compare/PWM (CCP) Module
- TABLE 9-1: CCP Mode - Timer Resource
- FIGURE 9-1: Capture Mode Operation Block Diagram
- FIGURE 9-2: Compare Mode Operation Block Diagram
- TABLE 9-2: Registers Associated with Capture, compare, and Timer1
- FIGURE 9-3: Simplified PWM Block Diagram
- FIGURE 9-4: PWM OUTPUT
- TABLE 9-3: Example PWM Frequencies and Resolutions at 20 MHz
- TABLE 9-4: Registers Associated with PWM and Timer2
- 10.0 Comparator Module
- 11.0 Voltage Reference Module
- 12.0 Universal Synchronous Asynchronous Receiver Transmitter (USART) Module
- TABLE 12-1: BAUD rATE fORMULA
- TABLE 12-2: Registers Associated with Baud Rate Generator
- TABLE 12-3: Baud Rates for synchronous Mode
- TABLE 12-4: Baud Rates for Asynchronous Mode (BRGH = 0)
- TABLE 12-5: Baud Rates for Asynchronous Mode (BRGH = 1)
- FIGURE 12-1: RX Pin Sampling Scheme. BRGH = 0
- FIGURE 12-2: RX Pin Sampling Scheme, BRGH = 1
- FIGURE 12-3: RX Pin Sampling Scheme, BRGH = 1
- FIGURE 12-4: RX Pin Sampling Scheme, BRGH = 0 OR BRGH = 1
- FIGURE 12-5: USART Transmit Block Diagram
- FIGURE 12-6: Asynchronous Transmission
- FIGURE 12-7: Asynchronous Transmission (Back to Back)
- TABLE 12-6: Registers Associated with Asynchronous Transmission
- FIGURE 12-8: USART Receive Block Diagram
- FIGURE 12-9: Asynchronous Reception with Address Detect
- FIGURE 12-10: Asynchronous Reception with Address Byte First
- FIGURE 12-11: Asynchronous Reception with Address Byte First Followed by Valid Data Byte
- TABLE 12-7: Registers Associated with Asynchronous Reception
- TABLE 12-8: Registers Associated with Asynchronous Reception
- TABLE 12-9: Registers Associated with Synchronous Master Transmission
- FIGURE 12-12: Synchronous Transmission
- FIGURE 12-13: Synchronous Transmission (Through TXEN)
- TABLE 12-10: Registers Associated with Synchronous Master Reception
- FIGURE 12-14: Synchronous Reception (Master Mode, SREN)
- TABLE 12-11: Registers Associated with Synchronous Slave Transmission
- TABLE 12-12: Registers Associated with Synchronous Slave Reception
- 13.0 Data EEPROM Memory
- 14.0 Special Features of the CPU
- FIGURE 14-1: Crystal Operation (or Ceramic Resonator) (HS, XT or LP Osc Configuration)
- TABLE 14-1: Capacitor Selection for Ceramic Resonators
- TABLE 14-2: Capacitor Selection for Crystal Oscillator
- FIGURE 14-2: External Parallel Resonant Crystal Oscillator Circuit
- FIGURE 14-3: External Series Resonant Crystal Oscillator Circuit
- FIGURE 14-4: External Clock Input Operation (EC, HS, XT or LP Osc Configuration)
- FIGURE 14-5: RC OSCILLATOR MODE
- FIGURE 14-6: Simplified Block Diagram of On-chip Reset Circuit
- FIGURE 14-7: Brown-out Situations WITH PWRT ENABLED
- TABLE 14-3: Time out in Various Situations
- TABLE 14-4: Status/PCON Bits and Their Significance
- TABLE 14-5: Summary of Registers Associated with Brown-out Reset
- TABLE 14-6: Initialization Condition for Special Registers
- TABLE 14-7: Initialization Condition for Registers
- FIGURE 14-8: Time out Sequence on Power-up (MCLR not tied to Vdd): Case
- FIGURE 14-9: Time out Sequence on Power-up (MCLR not tied to Vdd): Case 2
- FIGURE 14-10: Time out Sequence on Power-up (MCLR tied to Vdd)
- FIGURE 14-11: External Power-on Reset Circuit (For Slow Vdd Power-up)
- FIGURE 14-12: External Brown-out Protection Circuit 1
- FIGURE 14-13: External Brown-out Protection Circuit 2
- FIGURE 14-14: Interrupt Logic
- FIGURE 14-15: INT Pin Interrupt Timing
- TABLE 14-8: Summary of interrupt registers
- FIGURE 14-16: Watchdog Timer Block Diagram
- TABLE 14-9: Summary of Watchdog Timer Registers
- FIGURE 14-17: Wake-up from Sleep Through Interrupt
- FIGURE 14-18: Typical In-Circuit Serial Programming Connection
- 15.0 Instruction Set Summary
- 16.0 Development Support
- 17.0 Electrical Specifications
- FIGURE 17-1: PIC16F627A/628A/648A VOLTAGE-FREQUENCY GRAPH, -40°C £ TA £ +125°C
- FIGURE 17-2: PIC16LF627A/628A/648A VOLTAGE-FREQUENCY GRAPH, -40°C £ TA £ +85°C
- TABLE 17-1: DC Characteristics: PIC16F627A/628A/648A (Industrial, Extended) PIC16LF627A/628A/648A...
- TABLE 17-2: Comparator Specifications
- TABLE 17-3: Voltage Reference Specifications
- FIGURE 17-3: Load Conditions
- FIGURE 17-4: External Clock Timing
- TABLE 17-4: External Clock Timing Requirements
- TABLE 17-5: pRECISION INTERNAL OSCILLATOR Parameters
- FIGURE 17-5: CLKOUT and I/O Timing
- TABLE 17-6: CLKOUT and I/O Timing Requirements
- FIGURE 17-6: Reset, Watchdog Timer, Oscillator Start-Up Timer and Power-Up Timer Timing
- FIGURE 17-7: Brown-out Detect Timing
- TABLE 17-7: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Requirements
- FIGURE 17-8: Timer0 and Timer1 External Clock Timings
- TABLE 17-9: Timer0 and Timer1 External Clock Requirements
- FIGURE 17-10: Capture/Compare/PWM Timings
- TABLE 17-8: Capture/Compare/PWM Requirements
- FIGURE 17-11: TIMER0 Clock Timing
- TABLE 17-9: TIMER0 Clock Requirements
- 18.0 DC and AC Characteristics Graphs and Tables
- 19.0 Packaging Information
- Appendix A: Data Sheet Revision History
- Appendix B: Device Differences
- Appendix C: Device Migrations
- Appendix D: Migrating from other PICmicro Devices
- Appendix E: Development Tool Version Requirements
- Index
- Product ID System
- Worldwide Sales
PIC16F627A/628A/648A
DS40044A-page 162 Preliminary 2002 Microchip Technology Inc.
RB5 Pin............................................................... 40
RB6/T1OSO/T1CKI Pin ...................................... 41
RB7/T1OSI Pin ................................................... 42
PORTA ........................................................................ 31
PORTB........................................................................ 36
Programming Considerations ..................................... 44
Successive Operations ............................................... 44
TRISA ......................................................................... 31
TRISB ......................................................................... 36
ICEPIC In-Circuit Emulator ...............................................126
ID Locations ...................................................................... 108
INCF Instruction ................................................................ 118
INCFSZ Instruction............................................................ 118
In-Circuit Serial Programming ........................................... 109
Indirect Addressing, INDF and FSR Registers.................... 28
Instruction Flow/Pipelining .................................................. 13
Instruction Set
ADDLW ..................................................................... 113
ADDWF..................................................................... 113
ANDLW ..................................................................... 113
ANDWF..................................................................... 113
BCF........................................................................... 114
BSF ........................................................................... 114
BTFSC ......................................................................114
BTFSS ...................................................................... 115
CALL ......................................................................... 115
CLRF......................................................................... 115
CLRW........................................................................ 116
CLRWDT................................................................... 116
COMF ....................................................................... 116
DECF ........................................................................ 116
DECFSZ.................................................................... 117
GOTO........................................................................ 117
INCF.......................................................................... 118
INCFSZ ..................................................................... 118
IORLW....................................................................... 119
IORWF ...................................................................... 119
MOVF........................................................................ 119
MOVLW..................................................................... 119
MOVWF .................................................................... 120
NOP ..........................................................................120
OPTION ....................................................................120
RETFIE .....................................................................120
RETLW...................................................................... 121
RETURN ................................................................... 121
RLF ........................................................................... 121
RRF........................................................................... 122
SLEEP ...................................................................... 122
SUBLW...................................................................... 122
SUBWF ..................................................................... 123
SWAPF ..................................................................... 123
TRIS.......................................................................... 123
XORLW ..................................................................... 124
XORWF..................................................................... 124
Instruction Set Summary................................................... 111
INT Interrupt ...................................................................... 105
INTCON Register ................................................................ 24
Interrupt Sources
Capture Complete (CCP)............................................ 56
Compare Complete (CCP).......................................... 57
TMR2 to PR2 Match (PWM) ....................................... 58
Interrupts ........................................................................... 104
Interrupts, Enable Bits
CCP1 Enable (CCP1IE Bit)......................................... 56
Interrupts, Flag Bits
CCP1 Flag (CCP1IF Bit)............................................. 56
IORLW Instruction ............................................................ 119
IORWF Instruction ............................................................ 119
K
KeeLoq Evaluation and Programming Tools .................... 128
M
Memory Organization
Data EEPROM Memory.................................. 89, 91, 92
Migrating from other PICmicro Devices ............................ 156
MOVF Instruction.............................................................. 119
MOVLW Instruction........................................................... 119
MOVWF Instruction .......................................................... 120
MPLAB C17 and MPLAB C18 C Compilers ..................... 125
MPLAB ICD In-Circuit Debugger ...................................... 127
MPLAB ICE High Performance Universal In-Circuit Emulator
with MPLAB IDE ............................................................... 126
MPLAB Integrated Development Environment Software.. 125
MPLINK Object Linker/MPLIB Object Librarian ................ 126
N
NOP Instruction ................................................................ 120
O
OPTION Instruction .......................................................... 120
OPTION Register................................................................ 23
Oscillator Configurations..................................................... 95
Oscillator Start-up Timer (OST) .......................................... 98
P
Package Marking Information ........................................... 149
Packaging Information ...................................................... 149
PCL and PCLATH............................................................... 28
Stack ........................................................................... 28
PCON Register ................................................................... 27
PICDEM 1 Low Cost PICmicro Demonstration Board ...... 127
PICDEM 17 Demonstration Board.................................... 128
PICDEM 2 Low Cost PIC16CXX Demonstration Board ... 127
PICDEM 3 Low Cost PIC16CXXX Demonstration Board . 128
PICSTART Plus Entry Level Development Programmer.. 127
PIE1 Register...................................................................... 25
Pin Functions
RC6/TX/CK........................................................... 69–86
RC7/RX/DT........................................................... 69–86
PIR1 Register ..................................................................... 26
Port RB Interrupt............................................................... 105
PORTA ............................................................................... 31
PORTB ............................................................................... 36
Power Control/Status Register (PCON).............................. 99
Power-Down Mode (SLEEP) ............................................ 107
Power-On Reset (POR) ...................................................... 98
Power-up Timer (PWRT) .................................................... 98
PR2 Register ................................................................ 52, 58
PRO MATE II Universal Device Programmer ................... 127
Program Memory Organization........................................... 15
PWM (CCP Module) ........................................................... 58
Block Diagram ............................................................ 58
Simplified PWM .................................................. 58
CCPR1H:CCPR1L Registers...................................... 58
Duty Cycle .................................................................. 59
Example Frequencies/Resolutions ............................. 59
Period ......................................................................... 58
Set-Up for PWM Operation......................................... 59
TMR2 to PR2 Match ................................................... 58